Source file src/cmd/internal/obj/ppc64/asm9.go

     1  // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova.
     2  //
     3  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     4  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     5  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     6  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     7  //	Portions Copyright © 2004,2006 Bruce Ellis
     8  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     9  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
    10  //	Portions Copyright © 2009 The Go Authors. All rights reserved.
    11  //
    12  // Permission is hereby granted, free of charge, to any person obtaining a copy
    13  // of this software and associated documentation files (the "Software"), to deal
    14  // in the Software without restriction, including without limitation the rights
    15  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    16  // copies of the Software, and to permit persons to whom the Software is
    17  // furnished to do so, subject to the following conditions:
    18  //
    19  // The above copyright notice and this permission notice shall be included in
    20  // all copies or substantial portions of the Software.
    21  //
    22  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    23  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    24  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    25  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    26  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    27  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    28  // THE SOFTWARE.
    29  
    30  package ppc64
    31  
    32  import (
    33  	"cmd/internal/obj"
    34  	"cmd/internal/objabi"
    35  	"encoding/binary"
    36  	"fmt"
    37  	"internal/buildcfg"
    38  	"log"
    39  	"math"
    40  	"math/bits"
    41  	"sort"
    42  )
    43  
    44  // ctxt9 holds state while assembling a single function.
    45  // Each function gets a fresh ctxt9.
    46  // This allows for multiple functions to be safely concurrently assembled.
    47  type ctxt9 struct {
    48  	ctxt       *obj.Link
    49  	newprog    obj.ProgAlloc
    50  	cursym     *obj.LSym
    51  	autosize   int32
    52  	instoffset int64
    53  	pc         int64
    54  }
    55  
    56  // Instruction layout.
    57  
    58  const (
    59  	r0iszero = 1
    60  )
    61  
    62  const (
    63  	// R bit option in prefixed load/store/add D-form operations
    64  	PFX_R_ABS   = 0 // Offset is absolute
    65  	PFX_R_PCREL = 1 // Offset is relative to PC, RA should be 0
    66  )
    67  
    68  const (
    69  	// The preferred hardware nop instruction.
    70  	NOP = 0x60000000
    71  )
    72  
    73  type Optab struct {
    74  	as    obj.As // Opcode
    75  	a1    uint8  // p.From argument (obj.Addr). p is of type obj.Prog.
    76  	a2    uint8  // p.Reg argument (int16 Register)
    77  	a3    uint8  // p.RestArgs[0]  (obj.AddrPos)
    78  	a4    uint8  // p.RestArgs[1]
    79  	a5    uint8  // p.RestARgs[2]
    80  	a6    uint8  // p.To (obj.Addr)
    81  	type_ int8   // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r
    82  	size  int8   // Text space in bytes to lay operation
    83  
    84  	// A prefixed instruction is generated by this opcode. This cannot be placed
    85  	// across a 64B PC address. Opcodes should not translate to more than one
    86  	// prefixed instruction. The prefixed instruction should be written first
    87  	// (e.g when Optab.size > 8).
    88  	ispfx bool
    89  
    90  	asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32)
    91  }
    92  
    93  // optab contains an array to be sliced of accepted operand combinations for an
    94  // instruction. Unused arguments and fields are not explicitly enumerated, and
    95  // should not be listed for clarity. Unused arguments and values should always
    96  // assume the default value for the given type.
    97  //
    98  // optab does not list every valid ppc64 opcode, it enumerates representative
    99  // operand combinations for a class of instruction.  The variable oprange indexes
   100  // all valid ppc64 opcodes.
   101  //
   102  // oprange is initialized to point a slice within optab which contains the valid
   103  // operand combinations for a given instruction.  This is initialized from buildop.
   104  //
   105  // Likewise, each slice of optab is dynamically sorted using the ocmp Sort interface
   106  // to arrange entries to minimize text size of each opcode.
   107  //
   108  // optab is the sorted result of combining optabBase, optabGen, and prefixableOptab.
   109  var optab []Optab
   110  
   111  var optabBase = []Optab{
   112  	{as: obj.ATEXT, a1: C_LOREG, a6: C_TEXTSIZE, type_: 0, size: 0},
   113  	{as: obj.ATEXT, a1: C_LOREG, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
   114  	{as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE, type_: 0, size: 0},
   115  	{as: obj.ATEXT, a1: C_ADDR, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
   116  	/* move register */
   117  	{as: AADD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
   118  	{as: AADD, a1: C_REG, a6: C_REG, type_: 2, size: 4},
   119  	{as: AADD, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
   120  	{as: AADD, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
   121  	{as: AADD, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 22, size: 8},
   122  	{as: AADD, a1: C_U16CON, a6: C_REG, type_: 22, size: 8},
   123  	{as: AADDIS, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 20, size: 4},
   124  	{as: AADDIS, a1: C_S16CON, a6: C_REG, type_: 20, size: 4},
   125  	{as: AADDC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
   126  	{as: AADDC, a1: C_REG, a6: C_REG, type_: 2, size: 4},
   127  	{as: AADDC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
   128  	{as: AADDC, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
   129  	{as: AADDC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
   130  	{as: AADDC, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
   131  	{as: AAND, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, /* logical, no literal */
   132  	{as: AAND, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   133  	{as: AANDCC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   134  	{as: AANDCC, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   135  	{as: AANDCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
   136  	{as: AANDCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
   137  	{as: AANDCC, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
   138  	{as: AANDCC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
   139  	{as: AANDCC, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
   140  	{as: AANDCC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
   141  	{as: AANDISCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
   142  	{as: AANDISCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
   143  	{as: AMULLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
   144  	{as: AMULLW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
   145  	{as: AMULLW, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
   146  	{as: AMULLW, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
   147  	{as: AMULLW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
   148  	{as: AMULLW, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
   149  	{as: ASUBC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
   150  	{as: ASUBC, a1: C_REG, a6: C_REG, type_: 10, size: 4},
   151  	{as: ASUBC, a1: C_REG, a3: C_S16CON, a6: C_REG, type_: 27, size: 4},
   152  	{as: ASUBC, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 28, size: 12},
   153  	{as: AOR, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, /* logical, literal not cc (or/xor) */
   154  	{as: AOR, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   155  	{as: AOR, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
   156  	{as: AOR, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
   157  	{as: AOR, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
   158  	{as: AOR, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
   159  	{as: AOR, a1: C_U32CON, a2: C_REG, a6: C_REG, type_: 21, size: 8},
   160  	{as: AOR, a1: C_U32CON, a6: C_REG, type_: 21, size: 8},
   161  	{as: AOR, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
   162  	{as: AOR, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
   163  	{as: AORIS, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
   164  	{as: AORIS, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
   165  	{as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4}, /* op r1[,r2],r3 */
   166  	{as: ADIVW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
   167  	{as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4}, /* op r2[,r1],r3 */
   168  	{as: ASUB, a1: C_REG, a6: C_REG, type_: 10, size: 4},
   169  	{as: ASLW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   170  	{as: ASLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   171  	{as: ASLD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   172  	{as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   173  	{as: ASLD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
   174  	{as: ASLD, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
   175  	{as: AEXTSWSLI, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
   176  	{as: AEXTSWSLI, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
   177  	{as: ASLW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 57, size: 4},
   178  	{as: ASLW, a1: C_U15CON, a6: C_REG, type_: 57, size: 4},
   179  	{as: ASRAW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   180  	{as: ASRAW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   181  	{as: ASRAW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
   182  	{as: ASRAW, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
   183  	{as: ASRAD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
   184  	{as: ASRAD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
   185  	{as: ASRAD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
   186  	{as: ASRAD, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
   187  	{as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
   188  	{as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
   189  	{as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
   190  	{as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
   191  	{as: ACLRLSLWI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 62, size: 4},
   192  	{as: ARLDMI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 30, size: 4},
   193  	{as: ARLDC, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
   194  	{as: ARLDC, a1: C_REG, a3: C_U8CON, a4: C_U8CON, a6: C_REG, type_: 9, size: 4},
   195  	{as: ARLDCL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
   196  	{as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
   197  	{as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
   198  	{as: ARLDICL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
   199  	{as: ARLDCL, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
   200  	{as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4},
   201  	{as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4},
   202  	{as: ADADDQ, a1: C_FREGP, a6: C_FREGP, type_: 2, size: 4},
   203  	{as: ADADDQ, a1: C_FREGP, a2: C_FREGP, a6: C_FREGP, type_: 2, size: 4},
   204  	{as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
   205  	{as: AFABS, a6: C_FREG, type_: 33, size: 4},
   206  	{as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4},
   207  	{as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4},
   208  	{as: AFMUL, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 32, size: 4},
   209  	{as: ADMULQ, a1: C_FREGP, a6: C_FREGP, type_: 32, size: 4},
   210  	{as: ADMULQ, a1: C_FREGP, a2: C_FREGP, a6: C_FREGP, type_: 32, size: 4},
   211  
   212  	{as: AMOVBU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   213  	{as: AMOVBU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   214  	{as: AMOVBU, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
   215  	{as: AMOVBU, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
   216  
   217  	{as: AMOVBZU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   218  	{as: AMOVBZU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   219  	{as: AMOVBZU, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
   220  	{as: AMOVBZU, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
   221  
   222  	{as: AMOVHBR, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
   223  	{as: AMOVHBR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
   224  
   225  	{as: AMOVB, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
   226  	{as: AMOVB, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
   227  	{as: AMOVB, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   228  	{as: AMOVB, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   229  	{as: AMOVB, a1: C_REG, a6: C_REG, type_: 13, size: 4},
   230  
   231  	{as: AMOVBZ, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
   232  	{as: AMOVBZ, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
   233  	{as: AMOVBZ, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   234  	{as: AMOVBZ, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   235  	{as: AMOVBZ, a1: C_REG, a6: C_REG, type_: 13, size: 4},
   236  
   237  	{as: AMOVD, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
   238  	{as: AMOVD, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
   239  	{as: AMOVD, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
   240  	{as: AMOVD, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
   241  	{as: AMOVD, a1: C_SOREG, a6: C_SPR, type_: 107, size: 8},
   242  	{as: AMOVD, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
   243  	{as: AMOVD, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   244  	{as: AMOVD, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   245  	{as: AMOVD, a1: C_SPR, a6: C_SOREG, type_: 106, size: 8},
   246  	{as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
   247  	{as: AMOVD, a1: C_REG, a6: C_REG, type_: 13, size: 4},
   248  
   249  	{as: AMOVW, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
   250  	{as: AMOVW, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
   251  	{as: AMOVW, a1: C_CREG, a6: C_REG, type_: 68, size: 4},
   252  	{as: AMOVW, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
   253  	{as: AMOVW, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
   254  	{as: AMOVW, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
   255  	{as: AMOVW, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
   256  	{as: AMOVW, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
   257  	{as: AMOVW, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
   258  	{as: AMOVW, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
   259  	{as: AMOVW, a1: C_REG, a6: C_REG, type_: 13, size: 4},
   260  
   261  	{as: AFMOVD, a1: C_S16CON, a6: C_FREG, type_: 24, size: 8},
   262  	{as: AFMOVD, a1: C_SOREG, a6: C_FREG, type_: 8, size: 4},
   263  	{as: AFMOVD, a1: C_XOREG, a6: C_FREG, type_: 109, size: 4},
   264  	{as: AFMOVD, a1: C_ZCON, a6: C_FREG, type_: 24, size: 4},
   265  	{as: AFMOVD, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
   266  	{as: AFMOVD, a1: C_FREG, a6: C_SOREG, type_: 7, size: 4},
   267  	{as: AFMOVD, a1: C_FREG, a6: C_XOREG, type_: 108, size: 4},
   268  
   269  	{as: AFMOVSX, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
   270  	{as: AFMOVSX, a1: C_FREG, a6: C_XOREG, type_: 44, size: 4},
   271  
   272  	{as: AFMOVSZ, a1: C_ZOREG, a6: C_FREG, type_: 45, size: 4},
   273  	{as: AFMOVSZ, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
   274  
   275  	{as: AMOVFL, a1: C_CREG, a6: C_CREG, type_: 67, size: 4},
   276  	{as: AMOVFL, a1: C_FPSCR, a6: C_CREG, type_: 73, size: 4},
   277  	{as: AMOVFL, a1: C_FPSCR, a6: C_FREG, type_: 53, size: 4},
   278  	{as: AMOVFL, a1: C_FREG, a3: C_32CON, a6: C_FPSCR, type_: 64, size: 4},
   279  	{as: AMOVFL, a1: C_FREG, a6: C_FPSCR, type_: 64, size: 4},
   280  	{as: AMOVFL, a1: C_32CON, a6: C_FPSCR, type_: 65, size: 4},
   281  	{as: AMOVFL, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
   282  	{as: AMOVFL, a1: C_REG, a6: C_32CON, type_: 69, size: 4},
   283  
   284  	{as: ASYSCALL, type_: 5, size: 4},
   285  	{as: ASYSCALL, a1: C_REG, type_: 77, size: 12},
   286  	{as: ASYSCALL, a1: C_U15CON, type_: 77, size: 12},
   287  	{as: ABEQ, a6: C_BRA, type_: 16, size: 4},
   288  	{as: ABEQ, a1: C_CREG, a6: C_BRA, type_: 16, size: 4},
   289  	{as: ABEQ, a1: C_CREG, a6: C_LR, type_: 17, size: 4},
   290  	{as: ABR, a6: C_BRA, type_: 11, size: 4},                                         // b label
   291  	{as: ABR, a6: C_BRAPIC, type_: 11, size: 8},                                      // b label; nop
   292  	{as: ABR, a6: C_LR, type_: 18, size: 4},                                          // blr
   293  	{as: ABR, a6: C_CTR, type_: 18, size: 4},                                         // bctr
   294  	{as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_BRA, type_: 16, size: 4},              // bc bo, bi, label
   295  	{as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_LR, type_: 18, size: 4},               // bclr bo, bi
   296  	{as: ABC, a1: C_U15CON, a2: C_CRBIT, a3: C_U15CON, a6: C_LR, type_: 18, size: 4}, // bclr bo, bi, bh
   297  	{as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_CTR, type_: 18, size: 4},              // bcctr bo, bi
   298  	{as: ABDNZ, a6: C_BRA, type_: 16, size: 4},
   299  	{as: ASYNC, type_: 46, size: 4},
   300  	{as: AWORD, a1: C_32CON, type_: 40, size: 4},
   301  	{as: ADWORD, a1: C_64CON, type_: 31, size: 8},
   302  	{as: ADWORD, a1: C_LACON, type_: 31, size: 8},
   303  	{as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4},
   304  	{as: AEXTSB, a1: C_REG, a6: C_REG, type_: 48, size: 4},
   305  	{as: AEXTSB, a6: C_REG, type_: 48, size: 4},
   306  	{as: AISEL, a1: C_U5CON, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
   307  	{as: AISEL, a1: C_CRBIT, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
   308  	{as: ANEG, a1: C_REG, a6: C_REG, type_: 47, size: 4},
   309  	{as: ANEG, a6: C_REG, type_: 47, size: 4},
   310  	{as: AREM, a1: C_REG, a6: C_REG, type_: 50, size: 12},
   311  	{as: AREM, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 12},
   312  	{as: AREMU, a1: C_REG, a6: C_REG, type_: 50, size: 16},
   313  	{as: AREMU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 16},
   314  	{as: AREMD, a1: C_REG, a6: C_REG, type_: 51, size: 12},
   315  	{as: AREMD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 51, size: 12},
   316  	{as: AMTFSB0, a1: C_U15CON, type_: 52, size: 4},
   317  	/* Other ISA 2.05+ instructions */
   318  	{as: APOPCNTD, a1: C_REG, a6: C_REG, type_: 93, size: 4},            /* population count, x-form */
   319  	{as: ACMPB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 92, size: 4},    /* compare byte, x-form */
   320  	{as: ACMPEQB, a1: C_REG, a2: C_REG, a6: C_CREG, type_: 92, size: 4}, /* compare equal byte, x-form, ISA 3.0 */
   321  	{as: ACMPEQB, a1: C_REG, a6: C_REG, type_: 70, size: 4},
   322  	{as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_U15CON, type_: 92, size: 4},          /* floating test for sw divide, x-form */
   323  	{as: AFTSQRT, a1: C_FREG, a6: C_U15CON, type_: 93, size: 4},                     /* floating test for sw square root, x-form */
   324  	{as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4},                           /* copy/paste facility, x-form */
   325  	{as: ADARN, a1: C_U15CON, a6: C_REG, type_: 92, size: 4},                        /* deliver random number, x-form */
   326  	{as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4},   /* multiply-add high/low doubleword, va-form */
   327  	{as: AADDEX, a1: C_REG, a2: C_REG, a3: C_U15CON, a6: C_REG, type_: 94, size: 4}, /* add extended using alternate carry, z23-form */
   328  	{as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4},          /* logical ops for condition register bits xl-form */
   329  
   330  	/* Misc ISA 3.0 instructions */
   331  	{as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4},
   332  	{as: AVCLZLSBB, a1: C_VREG, a6: C_REG, type_: 85, size: 4},
   333  
   334  	/* Vector instructions */
   335  
   336  	/* Vector load */
   337  	{as: ALVEBX, a1: C_XOREG, a6: C_VREG, type_: 45, size: 4}, /* vector load, x-form */
   338  
   339  	/* Vector store */
   340  	{as: ASTVEBX, a1: C_VREG, a6: C_XOREG, type_: 44, size: 4}, /* vector store, x-form */
   341  
   342  	/* Vector logical */
   343  	{as: AVAND, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector and, vx-form */
   344  	{as: AVOR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},  /* vector or, vx-form */
   345  
   346  	/* Vector add */
   347  	{as: AVADDUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector add unsigned modulo, vx-form */
   348  	{as: AVADDCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector add & write carry unsigned, vx-form */
   349  	{as: AVADDUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector add unsigned saturate, vx-form */
   350  	{as: AVADDSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector add signed saturate, vx-form */
   351  	{as: AVADDE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector add extended, va-form */
   352  
   353  	/* Vector subtract */
   354  	{as: AVSUBUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector subtract unsigned modulo, vx-form */
   355  	{as: AVSUBCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector subtract & write carry unsigned, vx-form */
   356  	{as: AVSUBUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector subtract unsigned saturate, vx-form */
   357  	{as: AVSUBSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},            /* vector subtract signed saturate, vx-form */
   358  	{as: AVSUBE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector subtract extended, va-form */
   359  
   360  	/* Vector multiply */
   361  	{as: AVMULESB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},              /* vector multiply, vx-form */
   362  	{as: AVPMSUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},               /* vector polynomial multiply & sum, vx-form */
   363  	{as: AVMSUMUDM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector multiply-sum, va-form */
   364  
   365  	/* Vector rotate */
   366  	{as: AVR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector rotate, vx-form */
   367  
   368  	/* Vector shift */
   369  	{as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},                 /* vector shift, vx-form */
   370  	{as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},                /* vector shift algebraic, vx-form */
   371  	{as: AVSOI, a1: C_U16CON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector shift by octet immediate, va-form */
   372  
   373  	/* Vector count */
   374  	{as: AVCLZ, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},    /* vector count leading zeros, vx-form */
   375  	{as: AVPOPCNT, a1: C_VREG, a6: C_VREG, type_: 85, size: 4}, /* vector population count, vx-form */
   376  
   377  	/* Vector compare */
   378  	{as: AVCMPEQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},   /* vector compare equal, vc-form */
   379  	{as: AVCMPGT, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},   /* vector compare greater than, vc-form */
   380  	{as: AVCMPNEZB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector compare not equal, vx-form */
   381  
   382  	/* Vector merge */
   383  	{as: AVMRGOW, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector merge odd word, vx-form */
   384  
   385  	/* Vector permute */
   386  	{as: AVPERM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector permute, va-form */
   387  
   388  	/* Vector bit permute */
   389  	{as: AVBPERMQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector bit permute, vx-form */
   390  
   391  	/* Vector select */
   392  	{as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector select, va-form */
   393  
   394  	/* Vector splat */
   395  	{as: AVSPLTB, a1: C_S16CON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
   396  	{as: AVSPLTISB, a1: C_S16CON, a6: C_VREG, type_: 82, size: 4},
   397  
   398  	/* Vector AES */
   399  	{as: AVCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},  /* vector AES cipher, vx-form */
   400  	{as: AVNCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector AES inverse cipher, vx-form */
   401  	{as: AVSBOX, a1: C_VREG, a6: C_VREG, type_: 82, size: 4},              /* vector AES subbytes, vx-form */
   402  
   403  	/* Vector SHA */
   404  	{as: AVSHASIGMA, a1: C_U16CON, a2: C_VREG, a3: C_U16CON, a6: C_VREG, type_: 82, size: 4}, /* vector SHA sigma, vx-form */
   405  
   406  	/* VSX vector load */
   407  	{as: ALXVD2X, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},        /* vsx vector load, xx1-form */
   408  	{as: ALXV, a1: C_SOREG, a6: C_VSREG, type_: 96, size: 4},           /* vsx vector load, dq-form */
   409  	{as: ALXVL, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 98, size: 4}, /* vsx vector load length */
   410  
   411  	/* VSX vector store */
   412  	{as: ASTXVD2X, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},        /* vsx vector store, xx1-form */
   413  	{as: ASTXV, a1: C_VSREG, a6: C_SOREG, type_: 97, size: 4},           /* vsx vector store, dq-form */
   414  	{as: ASTXVL, a1: C_VSREG, a2: C_REG, a6: C_REG, type_: 99, size: 4}, /* vsx vector store with length x-form */
   415  
   416  	/* VSX scalar load */
   417  	{as: ALXSDX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4}, /* vsx scalar load, xx1-form */
   418  
   419  	/* VSX scalar store */
   420  	{as: ASTXSDX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4}, /* vsx scalar store, xx1-form */
   421  
   422  	/* VSX scalar as integer load */
   423  	{as: ALXSIWAX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4}, /* vsx scalar as integer load, xx1-form */
   424  
   425  	/* VSX scalar store as integer */
   426  	{as: ASTXSIWX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4}, /* vsx scalar as integer store, xx1-form */
   427  
   428  	/* VSX move from VSR */
   429  	{as: AMFVSRD, a1: C_VSREG, a6: C_REG, type_: 88, size: 4},
   430  	{as: AMFVSRD, a1: C_FREG, a6: C_REG, type_: 88, size: 4},
   431  
   432  	/* VSX move to VSR */
   433  	{as: AMTVSRD, a1: C_REG, a6: C_VSREG, type_: 104, size: 4},
   434  	{as: AMTVSRD, a1: C_REG, a6: C_FREG, type_: 104, size: 4},
   435  	{as: AMTVSRDD, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 104, size: 4},
   436  
   437  	/* VSX xx3-form */
   438  	{as: AXXLAND, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 90, size: 4},    /* vsx xx3-form (FPR usage) */
   439  	{as: AXXLAND, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4}, /* vsx xx3-form */
   440  
   441  	/* VSX select */
   442  	{as: AXXSEL, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a6: C_VSREG, type_: 91, size: 4}, /* vsx select, xx4-form */
   443  
   444  	/* VSX merge */
   445  	{as: AXXMRGHW, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4}, /* vsx merge, xx3-form */
   446  
   447  	/* VSX splat */
   448  	{as: AXXSPLTW, a1: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 89, size: 4}, /* vsx splat, xx2-form */
   449  	{as: AXXSPLTIB, a1: C_U15CON, a6: C_VSREG, type_: 100, size: 4},            /* vsx splat, xx2-form */
   450  
   451  	/* VSX permute */
   452  	{as: AXXPERM, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4}, /* vsx permute, xx3-form */
   453  
   454  	/* VSX shift */
   455  	{as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 90, size: 4}, /* vsx shift immediate, xx3-form */
   456  
   457  	/* VSX reverse bytes */
   458  	{as: AXXBRQ, a1: C_VSREG, a6: C_VSREG, type_: 101, size: 4}, /* vsx reverse bytes */
   459  
   460  	/* VSX scalar FP-FP conversion */
   461  	{as: AXSCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx scalar fp-fp conversion, xx2-form */
   462  
   463  	/* VSX vector FP-FP conversion */
   464  	{as: AXVCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx vector fp-fp conversion, xx2-form */
   465  
   466  	/* VSX scalar FP-integer conversion */
   467  	{as: AXSCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx scalar fp-integer conversion, xx2-form */
   468  
   469  	/* VSX scalar integer-FP conversion */
   470  	{as: AXSCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx scalar integer-fp conversion, xx2-form */
   471  
   472  	/* VSX vector FP-integer conversion */
   473  	{as: AXVCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx vector fp-integer conversion, xx2-form */
   474  
   475  	/* VSX vector integer-FP conversion */
   476  	{as: AXVCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx vector integer-fp conversion, xx2-form */
   477  
   478  	{as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4},
   479  	{as: ACMP, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
   480  	{as: ACMP, a1: C_REG, a6: C_S16CON, type_: 70, size: 4},
   481  	{as: ACMP, a1: C_REG, a2: C_CREG, a6: C_S16CON, type_: 70, size: 4},
   482  	{as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4},
   483  	{as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
   484  	{as: ACMPU, a1: C_REG, a6: C_U16CON, type_: 70, size: 4},
   485  	{as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_U16CON, type_: 70, size: 4},
   486  	{as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4},
   487  	{as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4},
   488  	{as: ADCMPOQ, a1: C_FREGP, a6: C_FREGP, type_: 70, size: 4},
   489  	{as: ADCMPOQ, a1: C_FREGP, a2: C_CREG, a6: C_FREGP, type_: 70, size: 4},
   490  	{as: ATW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 60, size: 4},
   491  	{as: ATW, a1: C_32CON, a2: C_REG, a6: C_S16CON, type_: 61, size: 4},
   492  	{as: ADCBF, a1: C_SOREG, type_: 43, size: 4},
   493  	{as: ADCBF, a1: C_XOREG, type_: 43, size: 4},
   494  	{as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_U15CON, type_: 43, size: 4},
   495  	{as: ADCBF, a1: C_SOREG, a6: C_U15CON, type_: 43, size: 4},
   496  	{as: ADCBF, a1: C_XOREG, a6: C_U15CON, type_: 43, size: 4},
   497  	{as: ASTDCCC, a1: C_REG, a2: C_REG, a6: C_XOREG, type_: 44, size: 4},
   498  	{as: ASTDCCC, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
   499  	{as: ALDAR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
   500  	{as: ALDAR, a1: C_XOREG, a3: C_U16CON, a6: C_REG, type_: 45, size: 4},
   501  	{as: AEIEIO, type_: 46, size: 4},
   502  	{as: ATLBIE, a1: C_REG, type_: 49, size: 4},
   503  	{as: ATLBIE, a1: C_U15CON, a6: C_REG, type_: 49, size: 4},
   504  	{as: ASLBMFEE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
   505  	{as: ASLBMTE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
   506  	{as: ASTSW, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
   507  	{as: ASTSW, a1: C_REG, a3: C_32CON, a6: C_ZOREG, type_: 41, size: 4},
   508  	{as: ALSW, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
   509  	{as: ALSW, a1: C_ZOREG, a3: C_32CON, a6: C_REG, type_: 42, size: 4},
   510  
   511  	{as: obj.AUNDEF, type_: 78, size: 4},
   512  	{as: obj.APCDATA, a1: C_32CON, a6: C_32CON, type_: 0, size: 0},
   513  	{as: obj.AFUNCDATA, a1: C_U15CON, a6: C_ADDR, type_: 0, size: 0},
   514  	{as: obj.ANOP, type_: 0, size: 0},
   515  	{as: obj.ANOP, a1: C_32CON, type_: 0, size: 0}, // NOP operand variations added for #40689
   516  	{as: obj.ANOP, a1: C_REG, type_: 0, size: 0},   // to preserve previous behavior
   517  	{as: obj.ANOP, a1: C_FREG, type_: 0, size: 0},
   518  	{as: obj.ADUFFZERO, a6: C_BRA, type_: 11, size: 4}, // same as ABR/ABL
   519  	{as: obj.ADUFFCOPY, a6: C_BRA, type_: 11, size: 4}, // same as ABR/ABL
   520  	{as: obj.APCALIGN, a1: C_32CON, type_: 0, size: 0}, // align code
   521  }
   522  
   523  // These are opcodes above which may generate different sequences depending on whether prefix opcode support
   524  // is available
   525  type PrefixableOptab struct {
   526  	Optab
   527  	minGOPPC64 int  // Minimum GOPPC64 required to support this.
   528  	pfxsize    int8 // Instruction sequence size when prefixed opcodes are used
   529  }
   530  
   531  // The prefixable optab entry contains the pseudo-opcodes which generate relocations, or may generate
   532  // a more efficient sequence of instructions if a prefixed version exists (ex. paddi instead of oris/ori/add).
   533  //
   534  // This table is meant to transform all sequences which might be TOC-relative into an equivalent PC-relative
   535  // sequence. It also encompasses several transformations which do not involve relocations, those could be
   536  // separated and applied to AIX and other non-ELF targets. Likewise, the prefixed forms do not have encoding
   537  // restrictions on the offset, so they are also used for static binary to allow better code generation. e.x
   538  //
   539  //	MOVD something-byte-aligned(Rx), Ry
   540  //	MOVD 3(Rx), Ry
   541  //
   542  // is allowed when the prefixed forms are used.
   543  //
   544  // This requires an ISA 3.1 compatible cpu (e.g Power10), and when linking externally an ELFv2 1.5 compliant.
   545  var prefixableOptab = []PrefixableOptab{
   546  	{Optab: Optab{as: AMOVD, a1: C_S34CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
   547  	{Optab: Optab{as: AMOVD, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
   548  	{Optab: Optab{as: AMOVD, a1: C_TLS_LE, a6: C_REG, type_: 79, size: 8}, minGOPPC64: 10, pfxsize: 8},
   549  	{Optab: Optab{as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 12}, minGOPPC64: 10, pfxsize: 12},
   550  	{Optab: Optab{as: AMOVD, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
   551  	{Optab: Optab{as: AMOVD, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
   552  	{Optab: Optab{as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   553  	{Optab: Optab{as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   554  
   555  	{Optab: Optab{as: AMOVW, a1: C_32CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
   556  	{Optab: Optab{as: AMOVW, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
   557  	{Optab: Optab{as: AMOVW, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
   558  	{Optab: Optab{as: AMOVW, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
   559  	{Optab: Optab{as: AMOVW, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   560  	{Optab: Optab{as: AMOVW, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   561  
   562  	{Optab: Optab{as: AMOVB, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   563  	{Optab: Optab{as: AMOVB, a1: C_LOREG, a6: C_REG, type_: 36, size: 12}, minGOPPC64: 10, pfxsize: 12},
   564  	{Optab: Optab{as: AMOVB, a1: C_ADDR, a6: C_REG, type_: 75, size: 12}, minGOPPC64: 10, pfxsize: 12},
   565  	{Optab: Optab{as: AMOVB, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   566  
   567  	{Optab: Optab{as: AMOVBZ, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
   568  	{Optab: Optab{as: AMOVBZ, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
   569  	{Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   570  	{Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   571  
   572  	{Optab: Optab{as: AFMOVD, a1: C_LOREG, a6: C_FREG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
   573  	{Optab: Optab{as: AFMOVD, a1: C_ADDR, a6: C_FREG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
   574  	{Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
   575  	{Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
   576  
   577  	{Optab: Optab{as: AADD, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
   578  	{Optab: Optab{as: AADD, a1: C_32CON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
   579  	{Optab: Optab{as: AADD, a1: C_S34CON, a2: C_REG, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
   580  	{Optab: Optab{as: AADD, a1: C_S34CON, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
   581  }
   582  
   583  var oprange [ALAST & obj.AMask][]Optab
   584  
   585  var xcmp [C_NCLASS][C_NCLASS]bool
   586  
   587  var pfxEnabled = false // ISA 3.1 prefixed instructions are supported.
   588  var buildOpCfg = ""    // Save the os/cpu/arch tuple used to configure the assembler in buildop
   589  
   590  // padding bytes to add to align code as requested.
   591  func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
   592  	switch a {
   593  	case 8, 16, 32, 64:
   594  		// By default function alignment is 16. If an alignment > 16 is
   595  		// requested then the function alignment must also be promoted.
   596  		// The function alignment is not promoted on AIX at this time.
   597  		// TODO: Investigate AIX function alignment.
   598  		if ctxt.Headtype != objabi.Haix && cursym.Func().Align < int32(a) {
   599  			cursym.Func().Align = int32(a)
   600  		}
   601  		if pc&(a-1) != 0 {
   602  			return int(a - (pc & (a - 1)))
   603  		}
   604  	default:
   605  		ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
   606  	}
   607  	return 0
   608  }
   609  
   610  func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
   611  	p := cursym.Func().Text
   612  	if p == nil || p.Link == nil { // handle external functions and ELF section symbols
   613  		return
   614  	}
   615  
   616  	if oprange[AANDN&obj.AMask] == nil {
   617  		ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
   618  	}
   619  
   620  	c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
   621  
   622  	pc := int64(0)
   623  	p.Pc = pc
   624  
   625  	var m int
   626  	var o *Optab
   627  	for p = p.Link; p != nil; p = p.Link {
   628  		p.Pc = pc
   629  		o = c.oplook(p)
   630  		m = int(o.size)
   631  		if m == 0 {
   632  			if p.As == obj.APCALIGN {
   633  				a := c.vregoff(&p.From)
   634  				m = addpad(pc, a, ctxt, cursym)
   635  			} else {
   636  				if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
   637  					ctxt.Diag("zero-width instruction\n%v", p)
   638  				}
   639  				continue
   640  			}
   641  		}
   642  		pc += int64(m)
   643  	}
   644  
   645  	c.cursym.Size = pc
   646  
   647  	/*
   648  	 * if any procedure is large enough to
   649  	 * generate a large SBRA branch, then
   650  	 * generate extra passes putting branches
   651  	 * around jmps to fix. this is rare.
   652  	 */
   653  	bflag := 1
   654  
   655  	var otxt int64
   656  	var q *obj.Prog
   657  	var out [5]uint32
   658  	var falign int32 // Track increased alignment requirements for prefix.
   659  	for bflag != 0 {
   660  		bflag = 0
   661  		pc = 0
   662  		falign = 0 // Note, linker bumps function symbols to funcAlign.
   663  		for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
   664  			p.Pc = pc
   665  			o = c.oplook(p)
   666  
   667  			// very large conditional branches
   668  			if (o.type_ == 16 || o.type_ == 17) && p.To.Target() != nil {
   669  				otxt = p.To.Target().Pc - pc
   670  				if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
   671  					// Assemble the instruction with a target not too far to figure out BI and BO fields.
   672  					// If only the CTR or BI (the CR bit) are tested, the conditional branch can be inverted,
   673  					// and only one extra branch is needed to reach the target.
   674  					tgt := p.To.Target()
   675  					p.To.SetTarget(p.Link)
   676  					o.asmout(&c, p, o, &out)
   677  					p.To.SetTarget(tgt)
   678  
   679  					bo := int64(out[0]>>21) & 31
   680  					bi := int16((out[0] >> 16) & 31)
   681  					invertible := false
   682  
   683  					if bo&0x14 == 0x14 {
   684  						// A conditional branch that is unconditionally taken. This cannot be inverted.
   685  					} else if bo&0x10 == 0x10 {
   686  						// A branch based on the value of CTR. Invert the CTR comparison against zero bit.
   687  						bo ^= 0x2
   688  						invertible = true
   689  					} else if bo&0x04 == 0x04 {
   690  						// A branch based on CR bit. Invert the BI comparison bit.
   691  						bo ^= 0x8
   692  						invertible = true
   693  					}
   694  
   695  					if invertible {
   696  						// Rewrite
   697  						//     BC bo,...,far_away_target
   698  						//     NEXT_INSN
   699  						// to:
   700  						//     BC invert(bo),next_insn
   701  						//     JMP far_away_target
   702  						//   next_insn:
   703  						//     NEXT_INSN
   704  						p.As = ABC
   705  						p.From = obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: bo}
   706  						q = c.newprog()
   707  						q.As = ABR
   708  						q.To.Type = obj.TYPE_BRANCH
   709  						q.To.SetTarget(p.To.Target())
   710  						q.Link = p.Link
   711  						p.To.SetTarget(p.Link)
   712  						p.Link = q
   713  						p.Reg = REG_CRBIT0 + bi
   714  					} else {
   715  						// Rewrite
   716  						//     BC ...,far_away_target
   717  						//     NEXT_INSN
   718  						// to
   719  						//     BC ...,tmp
   720  						//     JMP next_insn
   721  						//   tmp:
   722  						//     JMP far_away_target
   723  						//   next_insn:
   724  						//     NEXT_INSN
   725  						q = c.newprog()
   726  						q.Link = p.Link
   727  						p.Link = q
   728  						q.As = ABR
   729  						q.To.Type = obj.TYPE_BRANCH
   730  						q.To.SetTarget(p.To.Target())
   731  						p.To.SetTarget(q)
   732  						q = c.newprog()
   733  						q.Link = p.Link
   734  						p.Link = q
   735  						q.As = ABR
   736  						q.To.Type = obj.TYPE_BRANCH
   737  						q.To.SetTarget(q.Link.Link)
   738  					}
   739  					bflag = 1
   740  				}
   741  			}
   742  
   743  			m = int(o.size)
   744  			if m == 0 {
   745  				if p.As == obj.APCALIGN {
   746  					a := c.vregoff(&p.From)
   747  					m = addpad(pc, a, ctxt, cursym)
   748  				} else {
   749  					if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
   750  						ctxt.Diag("zero-width instruction\n%v", p)
   751  					}
   752  					continue
   753  				}
   754  			}
   755  
   756  			// Prefixed instructions cannot be placed across a 64B boundary.
   757  			// Mark and adjust the PC of those which do. A nop will be
   758  			// inserted during final assembly.
   759  			if o.ispfx {
   760  				mark := p.Mark &^ PFX_X64B
   761  				if pc&63 == 60 {
   762  					p.Pc += 4
   763  					m += 4
   764  					mark |= PFX_X64B
   765  				}
   766  
   767  				// Marks may be adjusted if a too-far conditional branch is
   768  				// fixed up above. Likewise, inserting a NOP may cause a
   769  				// branch target to become too far away.  We need to run
   770  				// another iteration and verify no additional changes
   771  				// are needed.
   772  				if mark != p.Mark {
   773  					bflag = 1
   774  					p.Mark = mark
   775  				}
   776  
   777  				// Check for 16 or 32B crossing of this prefixed insn.
   778  				// These do no require padding, but do require increasing
   779  				// the function alignment to prevent them from potentially
   780  				// crossing a 64B boundary when the linker assigns the final
   781  				// PC.
   782  				switch p.Pc & 31 {
   783  				case 28: // 32B crossing
   784  					falign = 64
   785  				case 12: // 16B crossing
   786  					if falign < 64 {
   787  						falign = 32
   788  					}
   789  				}
   790  			}
   791  
   792  			pc += int64(m)
   793  		}
   794  
   795  		c.cursym.Size = pc
   796  	}
   797  
   798  	c.cursym.Size = pc
   799  	c.cursym.Func().Align = falign
   800  	c.cursym.Grow(c.cursym.Size)
   801  
   802  	// lay out the code, emitting code and data relocations.
   803  
   804  	bp := c.cursym.P
   805  	var i int32
   806  	for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
   807  		c.pc = p.Pc
   808  		o = c.oplook(p)
   809  		if int(o.size) > 4*len(out) {
   810  			log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
   811  		}
   812  		// asmout is not set up to add large amounts of padding
   813  		if o.type_ == 0 && p.As == obj.APCALIGN {
   814  			aln := c.vregoff(&p.From)
   815  			v := addpad(p.Pc, aln, c.ctxt, c.cursym)
   816  			if v > 0 {
   817  				// Same padding instruction for all
   818  				for i = 0; i < int32(v/4); i++ {
   819  					c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
   820  					bp = bp[4:]
   821  				}
   822  			}
   823  		} else {
   824  			if p.Mark&PFX_X64B != 0 {
   825  				c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
   826  				bp = bp[4:]
   827  			}
   828  			o.asmout(&c, p, o, &out)
   829  			for i = 0; i < int32(o.size/4); i++ {
   830  				c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
   831  				bp = bp[4:]
   832  			}
   833  		}
   834  	}
   835  }
   836  
   837  func isint32(v int64) bool {
   838  	return int64(int32(v)) == v
   839  }
   840  
   841  func isuint32(v uint64) bool {
   842  	return uint64(uint32(v)) == v
   843  }
   844  
   845  func (c *ctxt9) aclassreg(reg int16) int {
   846  	if REG_R0 <= reg && reg <= REG_R31 {
   847  		return C_REGP + int(reg&1)
   848  	}
   849  	if REG_F0 <= reg && reg <= REG_F31 {
   850  		return C_FREGP + int(reg&1)
   851  	}
   852  	if REG_V0 <= reg && reg <= REG_V31 {
   853  		return C_VREG
   854  	}
   855  	if REG_VS0 <= reg && reg <= REG_VS63 {
   856  		return C_VSREGP + int(reg&1)
   857  	}
   858  	if REG_CR0 <= reg && reg <= REG_CR7 || reg == REG_CR {
   859  		return C_CREG
   860  	}
   861  	if REG_CR0LT <= reg && reg <= REG_CR7SO {
   862  		return C_CRBIT
   863  	}
   864  	if REG_SPR0 <= reg && reg <= REG_SPR0+1023 {
   865  		switch reg {
   866  		case REG_LR:
   867  			return C_LR
   868  
   869  		case REG_CTR:
   870  			return C_CTR
   871  		}
   872  
   873  		return C_SPR
   874  	}
   875  	if REG_A0 <= reg && reg <= REG_A7 {
   876  		return C_AREG
   877  	}
   878  	if reg == REG_FPSCR {
   879  		return C_FPSCR
   880  	}
   881  	return C_GOK
   882  }
   883  
   884  func (c *ctxt9) aclass(a *obj.Addr) int {
   885  	switch a.Type {
   886  	case obj.TYPE_NONE:
   887  		return C_NONE
   888  
   889  	case obj.TYPE_REG:
   890  		return c.aclassreg(a.Reg)
   891  
   892  	case obj.TYPE_MEM:
   893  		if a.Index != 0 {
   894  			if a.Name != obj.NAME_NONE || a.Offset != 0 {
   895  				c.ctxt.Logf("Unexpected Instruction operand index %d offset %d class %d \n", a.Index, a.Offset, a.Class)
   896  
   897  			}
   898  			return C_XOREG
   899  		}
   900  		switch a.Name {
   901  		case obj.NAME_GOTREF, obj.NAME_TOCREF:
   902  			return C_ADDR
   903  
   904  		case obj.NAME_EXTERN,
   905  			obj.NAME_STATIC:
   906  			c.instoffset = a.Offset
   907  			if a.Sym == nil {
   908  				break
   909  			} else if a.Sym.Type == objabi.STLSBSS {
   910  				// For PIC builds, use 12 byte got initial-exec TLS accesses.
   911  				if c.ctxt.Flag_shared {
   912  					return C_TLS_IE
   913  				}
   914  				// Otherwise, use 8 byte local-exec TLS accesses.
   915  				return C_TLS_LE
   916  			} else {
   917  				return C_ADDR
   918  			}
   919  
   920  		case obj.NAME_AUTO:
   921  			a.Reg = REGSP
   922  			c.instoffset = int64(c.autosize) + a.Offset
   923  			if c.instoffset >= -BIG && c.instoffset < BIG {
   924  				return C_SOREG
   925  			}
   926  			return C_LOREG
   927  
   928  		case obj.NAME_PARAM:
   929  			a.Reg = REGSP
   930  			c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
   931  			if c.instoffset >= -BIG && c.instoffset < BIG {
   932  				return C_SOREG
   933  			}
   934  			return C_LOREG
   935  
   936  		case obj.NAME_NONE:
   937  			c.instoffset = a.Offset
   938  			if a.Offset == 0 && a.Index == 0 {
   939  				return C_ZOREG
   940  			} else if c.instoffset >= -BIG && c.instoffset < BIG {
   941  				return C_SOREG
   942  			} else {
   943  				return C_LOREG
   944  			}
   945  		}
   946  
   947  		return C_GOK
   948  
   949  	case obj.TYPE_TEXTSIZE:
   950  		return C_TEXTSIZE
   951  
   952  	case obj.TYPE_FCONST:
   953  		// The only cases where FCONST will occur are with float64 +/- 0.
   954  		// All other float constants are generated in memory.
   955  		f64 := a.Val.(float64)
   956  		if f64 == 0 {
   957  			if math.Signbit(f64) {
   958  				return C_S16CON
   959  			}
   960  			return C_ZCON
   961  		}
   962  		log.Fatalf("Unexpected nonzero FCONST operand %v", a)
   963  
   964  	case obj.TYPE_CONST,
   965  		obj.TYPE_ADDR:
   966  		switch a.Name {
   967  		case obj.NAME_NONE:
   968  			c.instoffset = a.Offset
   969  			if a.Reg != 0 {
   970  				if -BIG <= c.instoffset && c.instoffset < BIG {
   971  					return C_SACON
   972  				}
   973  				if isint32(c.instoffset) {
   974  					return C_LACON
   975  				}
   976  				return C_DACON
   977  			}
   978  
   979  		case obj.NAME_EXTERN,
   980  			obj.NAME_STATIC:
   981  			s := a.Sym
   982  			if s == nil {
   983  				return C_GOK
   984  			}
   985  			c.instoffset = a.Offset
   986  			return C_LACON
   987  
   988  		case obj.NAME_AUTO:
   989  			a.Reg = REGSP
   990  			c.instoffset = int64(c.autosize) + a.Offset
   991  			if c.instoffset >= -BIG && c.instoffset < BIG {
   992  				return C_SACON
   993  			}
   994  			return C_LACON
   995  
   996  		case obj.NAME_PARAM:
   997  			a.Reg = REGSP
   998  			c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
   999  			if c.instoffset >= -BIG && c.instoffset < BIG {
  1000  				return C_SACON
  1001  			}
  1002  			return C_LACON
  1003  
  1004  		default:
  1005  			return C_GOK
  1006  		}
  1007  
  1008  		if c.instoffset >= 0 {
  1009  			sbits := bits.Len64(uint64(c.instoffset))
  1010  			switch {
  1011  			case sbits <= 5:
  1012  				return C_ZCON + sbits
  1013  			case sbits <= 8:
  1014  				return C_U8CON
  1015  			case sbits <= 15:
  1016  				return C_U15CON
  1017  			case sbits <= 16:
  1018  				return C_U16CON
  1019  			case sbits <= 31:
  1020  				return C_U31CON
  1021  			case sbits <= 32:
  1022  				return C_U32CON
  1023  			case sbits <= 33:
  1024  				return C_S34CON
  1025  			default:
  1026  				return C_64CON
  1027  			}
  1028  		} else {
  1029  			sbits := bits.Len64(uint64(^c.instoffset))
  1030  			switch {
  1031  			case sbits <= 15:
  1032  				return C_S16CON
  1033  			case sbits <= 31:
  1034  				return C_S32CON
  1035  			case sbits <= 33:
  1036  				return C_S34CON
  1037  			default:
  1038  				return C_64CON
  1039  			}
  1040  		}
  1041  
  1042  	case obj.TYPE_BRANCH:
  1043  		if a.Sym != nil && c.ctxt.Flag_dynlink && !pfxEnabled {
  1044  			return C_BRAPIC
  1045  		}
  1046  		return C_BRA
  1047  	}
  1048  
  1049  	return C_GOK
  1050  }
  1051  
  1052  func prasm(p *obj.Prog) {
  1053  	fmt.Printf("%v\n", p)
  1054  }
  1055  
  1056  func (c *ctxt9) oplook(p *obj.Prog) *Optab {
  1057  	a1 := int(p.Optab)
  1058  	if a1 != 0 {
  1059  		return &optab[a1-1]
  1060  	}
  1061  	a1 = int(p.From.Class)
  1062  	if a1 == 0 {
  1063  		a1 = c.aclass(&p.From) + 1
  1064  		p.From.Class = int8(a1)
  1065  	}
  1066  	a1--
  1067  
  1068  	argsv := [3]int{C_NONE + 1, C_NONE + 1, C_NONE + 1}
  1069  	for i, ap := range p.RestArgs {
  1070  		argsv[i] = int(ap.Addr.Class)
  1071  		if argsv[i] == 0 {
  1072  			argsv[i] = c.aclass(&ap.Addr) + 1
  1073  			ap.Addr.Class = int8(argsv[i])
  1074  		}
  1075  
  1076  	}
  1077  	a3 := argsv[0] - 1
  1078  	a4 := argsv[1] - 1
  1079  	a5 := argsv[2] - 1
  1080  
  1081  	a6 := int(p.To.Class)
  1082  	if a6 == 0 {
  1083  		a6 = c.aclass(&p.To) + 1
  1084  		p.To.Class = int8(a6)
  1085  	}
  1086  	a6--
  1087  
  1088  	a2 := C_NONE
  1089  	if p.Reg != 0 {
  1090  		a2 = c.aclassreg(p.Reg)
  1091  	}
  1092  
  1093  	// c.ctxt.Logf("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4, a5, a6)
  1094  	ops := oprange[p.As&obj.AMask]
  1095  	c1 := &xcmp[a1]
  1096  	c2 := &xcmp[a2]
  1097  	c3 := &xcmp[a3]
  1098  	c4 := &xcmp[a4]
  1099  	c5 := &xcmp[a5]
  1100  	c6 := &xcmp[a6]
  1101  	for i := range ops {
  1102  		op := &ops[i]
  1103  		if c1[op.a1] && c2[op.a2] && c3[op.a3] && c4[op.a4] && c5[op.a5] && c6[op.a6] {
  1104  			p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
  1105  			return op
  1106  		}
  1107  	}
  1108  
  1109  	c.ctxt.Diag("illegal combination %v %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5), DRconv(a6))
  1110  	prasm(p)
  1111  	if ops == nil {
  1112  		ops = optab
  1113  	}
  1114  	return &ops[0]
  1115  }
  1116  
  1117  // Compare two operand types (ex C_REG, or C_U15CON)
  1118  // and return true if b is compatible with a.
  1119  //
  1120  // Argument comparison isn't reflexitive, so care must be taken.
  1121  // a is the argument type as found in optab, b is the argument as
  1122  // fitted by aclass.
  1123  func cmp(a int, b int) bool {
  1124  	if a == b {
  1125  		return true
  1126  	}
  1127  	switch a {
  1128  
  1129  	case C_SPR:
  1130  		if b == C_LR || b == C_CTR {
  1131  			return true
  1132  		}
  1133  
  1134  	case C_U1CON:
  1135  		return cmp(C_ZCON, b)
  1136  	case C_U2CON:
  1137  		return cmp(C_U1CON, b)
  1138  	case C_U3CON:
  1139  		return cmp(C_U2CON, b)
  1140  	case C_U4CON:
  1141  		return cmp(C_U3CON, b)
  1142  	case C_U5CON:
  1143  		return cmp(C_U4CON, b)
  1144  	case C_U8CON:
  1145  		return cmp(C_U5CON, b)
  1146  	case C_U15CON:
  1147  		return cmp(C_U8CON, b)
  1148  	case C_S16CON:
  1149  		return cmp(C_U15CON, b)
  1150  	case C_U16CON:
  1151  		return cmp(C_U15CON, b)
  1152  	case C_16CON:
  1153  		return cmp(C_S16CON, b) || cmp(C_U16CON, b)
  1154  	case C_U31CON:
  1155  		return cmp(C_U16CON, b)
  1156  	case C_U32CON:
  1157  		return cmp(C_U31CON, b)
  1158  	case C_S32CON:
  1159  		return cmp(C_U31CON, b) || cmp(C_S16CON, b)
  1160  	case C_32CON:
  1161  		return cmp(C_S32CON, b) || cmp(C_U32CON, b)
  1162  	case C_S34CON:
  1163  		return cmp(C_32CON, b)
  1164  	case C_64CON:
  1165  		return cmp(C_S34CON, b)
  1166  
  1167  	case C_LACON:
  1168  		return cmp(C_SACON, b)
  1169  
  1170  	case C_SOREG:
  1171  		return cmp(C_ZOREG, b)
  1172  
  1173  	case C_LOREG:
  1174  		return cmp(C_SOREG, b)
  1175  
  1176  	case C_XOREG:
  1177  		return cmp(C_REG, b) || cmp(C_ZOREG, b)
  1178  
  1179  	// An even/odd register input always matches the regular register types.
  1180  	case C_REG:
  1181  		return cmp(C_REGP, b) || (b == C_ZCON && r0iszero != 0)
  1182  	case C_FREG:
  1183  		return cmp(C_FREGP, b)
  1184  	case C_VSREG:
  1185  		/* Allow any VR argument as a VSR operand. */
  1186  		return cmp(C_VSREGP, b) || cmp(C_VREG, b)
  1187  
  1188  	case C_ANY:
  1189  		return true
  1190  	}
  1191  
  1192  	return false
  1193  }
  1194  
  1195  // Used when sorting the optab. Sorting is
  1196  // done in a way so that the best choice of
  1197  // opcode/operand combination is considered first.
  1198  func optabLess(i, j int) bool {
  1199  	p1 := &optab[i]
  1200  	p2 := &optab[j]
  1201  	n := int(p1.as) - int(p2.as)
  1202  	// same opcode
  1203  	if n != 0 {
  1204  		return n < 0
  1205  	}
  1206  	// Consider those that generate fewer
  1207  	// instructions first.
  1208  	n = int(p1.size) - int(p2.size)
  1209  	if n != 0 {
  1210  		return n < 0
  1211  	}
  1212  	// operand order should match
  1213  	// better choices first
  1214  	n = int(p1.a1) - int(p2.a1)
  1215  	if n != 0 {
  1216  		return n < 0
  1217  	}
  1218  	n = int(p1.a2) - int(p2.a2)
  1219  	if n != 0 {
  1220  		return n < 0
  1221  	}
  1222  	n = int(p1.a3) - int(p2.a3)
  1223  	if n != 0 {
  1224  		return n < 0
  1225  	}
  1226  	n = int(p1.a4) - int(p2.a4)
  1227  	if n != 0 {
  1228  		return n < 0
  1229  	}
  1230  	n = int(p1.a5) - int(p2.a5)
  1231  	if n != 0 {
  1232  		return n < 0
  1233  	}
  1234  	n = int(p1.a6) - int(p2.a6)
  1235  	if n != 0 {
  1236  		return n < 0
  1237  	}
  1238  	return false
  1239  }
  1240  
  1241  // Add an entry to the opcode table for
  1242  // a new opcode b0 with the same operand combinations
  1243  // as opcode a.
  1244  func opset(a, b0 obj.As) {
  1245  	oprange[a&obj.AMask] = oprange[b0]
  1246  }
  1247  
  1248  // Determine if the build configuration requires a TOC pointer.
  1249  // It is assumed this always called after buildop.
  1250  func NeedTOCpointer(ctxt *obj.Link) bool {
  1251  	return !pfxEnabled && ctxt.Flag_shared
  1252  }
  1253  
  1254  // Build the opcode table
  1255  func buildop(ctxt *obj.Link) {
  1256  	// Limit PC-relative prefix instruction usage to supported and tested targets.
  1257  	pfxEnabled = buildcfg.GOPPC64 >= 10 && buildcfg.GOOS == "linux"
  1258  	cfg := fmt.Sprintf("power%d/%s/%s", buildcfg.GOPPC64, buildcfg.GOARCH, buildcfg.GOOS)
  1259  	if cfg == buildOpCfg {
  1260  		// Already initialized to correct OS/cpu; stop now.
  1261  		// This happens in the cmd/asm tests,
  1262  		// each of which re-initializes the arch.
  1263  		return
  1264  	}
  1265  	buildOpCfg = cfg
  1266  
  1267  	// Configure the optab entries which may generate prefix opcodes.
  1268  	prefixOptab := make([]Optab, 0, len(prefixableOptab))
  1269  	for _, entry := range prefixableOptab {
  1270  		entry := entry
  1271  		if pfxEnabled && buildcfg.GOPPC64 >= entry.minGOPPC64 {
  1272  			// Enable prefix opcode generation and resize.
  1273  			entry.ispfx = true
  1274  			entry.size = entry.pfxsize
  1275  		}
  1276  		prefixOptab = append(prefixOptab, entry.Optab)
  1277  
  1278  	}
  1279  
  1280  	for i := 0; i < C_NCLASS; i++ {
  1281  		for n := 0; n < C_NCLASS; n++ {
  1282  			if cmp(n, i) {
  1283  				xcmp[i][n] = true
  1284  			}
  1285  		}
  1286  	}
  1287  
  1288  	// Append the generated entries, sort, and fill out oprange.
  1289  	optab = make([]Optab, 0, len(optabBase)+len(optabGen)+len(prefixOptab))
  1290  	optab = append(optab, optabBase...)
  1291  	optab = append(optab, optabGen...)
  1292  	optab = append(optab, prefixOptab...)
  1293  	sort.Slice(optab, optabLess)
  1294  
  1295  	for i := range optab {
  1296  		// Use the legacy assembler function if none provided.
  1297  		if optab[i].asmout == nil {
  1298  			optab[i].asmout = asmout
  1299  		}
  1300  	}
  1301  
  1302  	for i := 0; i < len(optab); {
  1303  		r := optab[i].as
  1304  		r0 := r & obj.AMask
  1305  		start := i
  1306  		for i < len(optab) && optab[i].as == r {
  1307  			i++
  1308  		}
  1309  		oprange[r0] = optab[start:i]
  1310  
  1311  		switch r {
  1312  		default:
  1313  			if !opsetGen(r) {
  1314  				ctxt.Diag("unknown op in build: %v", r)
  1315  				log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
  1316  			}
  1317  
  1318  		case ADCBF: /* unary indexed: op (b+a); op (b) */
  1319  			opset(ADCBI, r0)
  1320  
  1321  			opset(ADCBST, r0)
  1322  			opset(ADCBT, r0)
  1323  			opset(ADCBTST, r0)
  1324  			opset(ADCBZ, r0)
  1325  			opset(AICBI, r0)
  1326  
  1327  		case ASTDCCC: /* indexed store: op s,(b+a); op s,(b) */
  1328  			opset(ASTWCCC, r0)
  1329  			opset(ASTHCCC, r0)
  1330  			opset(ASTBCCC, r0)
  1331  
  1332  		case AREM: /* macro */
  1333  			opset(AREM, r0)
  1334  
  1335  		case AREMU:
  1336  			opset(AREMU, r0)
  1337  
  1338  		case AREMD:
  1339  			opset(AREMDU, r0)
  1340  
  1341  		case AMULLW:
  1342  			opset(AMULLD, r0)
  1343  
  1344  		case ADIVW: /* op Rb[,Ra],Rd */
  1345  			opset(AMULHW, r0)
  1346  
  1347  			opset(AMULHWCC, r0)
  1348  			opset(AMULHWU, r0)
  1349  			opset(AMULHWUCC, r0)
  1350  			opset(AMULLWCC, r0)
  1351  			opset(AMULLWVCC, r0)
  1352  			opset(AMULLWV, r0)
  1353  			opset(ADIVWCC, r0)
  1354  			opset(ADIVWV, r0)
  1355  			opset(ADIVWVCC, r0)
  1356  			opset(ADIVWU, r0)
  1357  			opset(ADIVWUCC, r0)
  1358  			opset(ADIVWUV, r0)
  1359  			opset(ADIVWUVCC, r0)
  1360  			opset(AMODUD, r0)
  1361  			opset(AMODUW, r0)
  1362  			opset(AMODSD, r0)
  1363  			opset(AMODSW, r0)
  1364  			opset(AADDCC, r0)
  1365  			opset(AADDCV, r0)
  1366  			opset(AADDCVCC, r0)
  1367  			opset(AADDV, r0)
  1368  			opset(AADDVCC, r0)
  1369  			opset(AADDE, r0)
  1370  			opset(AADDECC, r0)
  1371  			opset(AADDEV, r0)
  1372  			opset(AADDEVCC, r0)
  1373  			opset(AMULHD, r0)
  1374  			opset(AMULHDCC, r0)
  1375  			opset(AMULHDU, r0)
  1376  			opset(AMULHDUCC, r0)
  1377  			opset(AMULLDCC, r0)
  1378  			opset(AMULLDVCC, r0)
  1379  			opset(AMULLDV, r0)
  1380  			opset(ADIVD, r0)
  1381  			opset(ADIVDCC, r0)
  1382  			opset(ADIVDE, r0)
  1383  			opset(ADIVDEU, r0)
  1384  			opset(ADIVDECC, r0)
  1385  			opset(ADIVDEUCC, r0)
  1386  			opset(ADIVDVCC, r0)
  1387  			opset(ADIVDV, r0)
  1388  			opset(ADIVDU, r0)
  1389  			opset(ADIVDUV, r0)
  1390  			opset(ADIVDUVCC, r0)
  1391  			opset(ADIVDUCC, r0)
  1392  
  1393  		case ACRAND:
  1394  			opset(ACRANDN, r0)
  1395  			opset(ACREQV, r0)
  1396  			opset(ACRNAND, r0)
  1397  			opset(ACRNOR, r0)
  1398  			opset(ACROR, r0)
  1399  			opset(ACRORN, r0)
  1400  			opset(ACRXOR, r0)
  1401  
  1402  		case APOPCNTD: /* popcntd, popcntw, popcntb, cnttzw, cnttzd */
  1403  			opset(APOPCNTW, r0)
  1404  			opset(APOPCNTB, r0)
  1405  			opset(ACNTTZW, r0)
  1406  			opset(ACNTTZWCC, r0)
  1407  			opset(ACNTTZD, r0)
  1408  			opset(ACNTTZDCC, r0)
  1409  
  1410  		case ACOPY: /* copy, paste. */
  1411  			opset(APASTECC, r0)
  1412  
  1413  		case AMADDHD: /* maddhd, maddhdu, maddld */
  1414  			opset(AMADDHDU, r0)
  1415  			opset(AMADDLD, r0)
  1416  
  1417  		case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */
  1418  			opset(AMOVH, r0)
  1419  			opset(AMOVHZ, r0)
  1420  
  1421  		case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */
  1422  			opset(AMOVHU, r0)
  1423  
  1424  			opset(AMOVHZU, r0)
  1425  			opset(AMOVWU, r0)
  1426  			opset(AMOVWZU, r0)
  1427  			opset(AMOVDU, r0)
  1428  			opset(AMOVMW, r0)
  1429  
  1430  		case ALVEBX: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */
  1431  			opset(ALVEHX, r0)
  1432  			opset(ALVEWX, r0)
  1433  			opset(ALVX, r0)
  1434  			opset(ALVXL, r0)
  1435  			opset(ALVSL, r0)
  1436  			opset(ALVSR, r0)
  1437  
  1438  		case ASTVEBX: /* stvebx, stvehx, stvewx, stvx, stvxl */
  1439  			opset(ASTVEHX, r0)
  1440  			opset(ASTVEWX, r0)
  1441  			opset(ASTVX, r0)
  1442  			opset(ASTVXL, r0)
  1443  
  1444  		case AVAND: /* vand, vandc, vnand */
  1445  			opset(AVAND, r0)
  1446  			opset(AVANDC, r0)
  1447  			opset(AVNAND, r0)
  1448  
  1449  		case AVMRGOW: /* vmrgew, vmrgow */
  1450  			opset(AVMRGEW, r0)
  1451  
  1452  		case AVOR: /* vor, vorc, vxor, vnor, veqv */
  1453  			opset(AVOR, r0)
  1454  			opset(AVORC, r0)
  1455  			opset(AVXOR, r0)
  1456  			opset(AVNOR, r0)
  1457  			opset(AVEQV, r0)
  1458  
  1459  		case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */
  1460  			opset(AVADDUBM, r0)
  1461  			opset(AVADDUHM, r0)
  1462  			opset(AVADDUWM, r0)
  1463  			opset(AVADDUDM, r0)
  1464  			opset(AVADDUQM, r0)
  1465  
  1466  		case AVADDCU: /* vaddcuq, vaddcuw */
  1467  			opset(AVADDCUQ, r0)
  1468  			opset(AVADDCUW, r0)
  1469  
  1470  		case AVADDUS: /* vaddubs, vadduhs, vadduws */
  1471  			opset(AVADDUBS, r0)
  1472  			opset(AVADDUHS, r0)
  1473  			opset(AVADDUWS, r0)
  1474  
  1475  		case AVADDSS: /* vaddsbs, vaddshs, vaddsws */
  1476  			opset(AVADDSBS, r0)
  1477  			opset(AVADDSHS, r0)
  1478  			opset(AVADDSWS, r0)
  1479  
  1480  		case AVADDE: /* vaddeuqm, vaddecuq */
  1481  			opset(AVADDEUQM, r0)
  1482  			opset(AVADDECUQ, r0)
  1483  
  1484  		case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */
  1485  			opset(AVSUBUBM, r0)
  1486  			opset(AVSUBUHM, r0)
  1487  			opset(AVSUBUWM, r0)
  1488  			opset(AVSUBUDM, r0)
  1489  			opset(AVSUBUQM, r0)
  1490  
  1491  		case AVSUBCU: /* vsubcuq, vsubcuw */
  1492  			opset(AVSUBCUQ, r0)
  1493  			opset(AVSUBCUW, r0)
  1494  
  1495  		case AVSUBUS: /* vsububs, vsubuhs, vsubuws */
  1496  			opset(AVSUBUBS, r0)
  1497  			opset(AVSUBUHS, r0)
  1498  			opset(AVSUBUWS, r0)
  1499  
  1500  		case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */
  1501  			opset(AVSUBSBS, r0)
  1502  			opset(AVSUBSHS, r0)
  1503  			opset(AVSUBSWS, r0)
  1504  
  1505  		case AVSUBE: /* vsubeuqm, vsubecuq */
  1506  			opset(AVSUBEUQM, r0)
  1507  			opset(AVSUBECUQ, r0)
  1508  
  1509  		case AVMULESB: /* vmulesb, vmulosb, vmuleub, vmuloub, vmulosh, vmulouh, vmulesw, vmulosw, vmuleuw, vmulouw, vmuluwm */
  1510  			opset(AVMULOSB, r0)
  1511  			opset(AVMULEUB, r0)
  1512  			opset(AVMULOUB, r0)
  1513  			opset(AVMULESH, r0)
  1514  			opset(AVMULOSH, r0)
  1515  			opset(AVMULEUH, r0)
  1516  			opset(AVMULOUH, r0)
  1517  			opset(AVMULESW, r0)
  1518  			opset(AVMULOSW, r0)
  1519  			opset(AVMULEUW, r0)
  1520  			opset(AVMULOUW, r0)
  1521  			opset(AVMULUWM, r0)
  1522  		case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */
  1523  			opset(AVPMSUMB, r0)
  1524  			opset(AVPMSUMH, r0)
  1525  			opset(AVPMSUMW, r0)
  1526  			opset(AVPMSUMD, r0)
  1527  
  1528  		case AVR: /* vrlb, vrlh, vrlw, vrld */
  1529  			opset(AVRLB, r0)
  1530  			opset(AVRLH, r0)
  1531  			opset(AVRLW, r0)
  1532  			opset(AVRLD, r0)
  1533  
  1534  		case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */
  1535  			opset(AVSLB, r0)
  1536  			opset(AVSLH, r0)
  1537  			opset(AVSLW, r0)
  1538  			opset(AVSL, r0)
  1539  			opset(AVSLO, r0)
  1540  			opset(AVSRB, r0)
  1541  			opset(AVSRH, r0)
  1542  			opset(AVSRW, r0)
  1543  			opset(AVSR, r0)
  1544  			opset(AVSRO, r0)
  1545  			opset(AVSLD, r0)
  1546  			opset(AVSRD, r0)
  1547  
  1548  		case AVSA: /* vsrab, vsrah, vsraw, vsrad */
  1549  			opset(AVSRAB, r0)
  1550  			opset(AVSRAH, r0)
  1551  			opset(AVSRAW, r0)
  1552  			opset(AVSRAD, r0)
  1553  
  1554  		case AVSOI: /* vsldoi */
  1555  			opset(AVSLDOI, r0)
  1556  
  1557  		case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */
  1558  			opset(AVCLZB, r0)
  1559  			opset(AVCLZH, r0)
  1560  			opset(AVCLZW, r0)
  1561  			opset(AVCLZD, r0)
  1562  
  1563  		case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */
  1564  			opset(AVPOPCNTB, r0)
  1565  			opset(AVPOPCNTH, r0)
  1566  			opset(AVPOPCNTW, r0)
  1567  			opset(AVPOPCNTD, r0)
  1568  
  1569  		case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */
  1570  			opset(AVCMPEQUB, r0)
  1571  			opset(AVCMPEQUBCC, r0)
  1572  			opset(AVCMPEQUH, r0)
  1573  			opset(AVCMPEQUHCC, r0)
  1574  			opset(AVCMPEQUW, r0)
  1575  			opset(AVCMPEQUWCC, r0)
  1576  			opset(AVCMPEQUD, r0)
  1577  			opset(AVCMPEQUDCC, r0)
  1578  
  1579  		case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */
  1580  			opset(AVCMPGTUB, r0)
  1581  			opset(AVCMPGTUBCC, r0)
  1582  			opset(AVCMPGTUH, r0)
  1583  			opset(AVCMPGTUHCC, r0)
  1584  			opset(AVCMPGTUW, r0)
  1585  			opset(AVCMPGTUWCC, r0)
  1586  			opset(AVCMPGTUD, r0)
  1587  			opset(AVCMPGTUDCC, r0)
  1588  			opset(AVCMPGTSB, r0)
  1589  			opset(AVCMPGTSBCC, r0)
  1590  			opset(AVCMPGTSH, r0)
  1591  			opset(AVCMPGTSHCC, r0)
  1592  			opset(AVCMPGTSW, r0)
  1593  			opset(AVCMPGTSWCC, r0)
  1594  			opset(AVCMPGTSD, r0)
  1595  			opset(AVCMPGTSDCC, r0)
  1596  
  1597  		case AVCMPNEZB: /* vcmpnezb[.] */
  1598  			opset(AVCMPNEZBCC, r0)
  1599  			opset(AVCMPNEB, r0)
  1600  			opset(AVCMPNEBCC, r0)
  1601  			opset(AVCMPNEH, r0)
  1602  			opset(AVCMPNEHCC, r0)
  1603  			opset(AVCMPNEW, r0)
  1604  			opset(AVCMPNEWCC, r0)
  1605  
  1606  		case AVPERM: /* vperm */
  1607  			opset(AVPERMXOR, r0)
  1608  			opset(AVPERMR, r0)
  1609  
  1610  		case AVBPERMQ: /* vbpermq, vbpermd */
  1611  			opset(AVBPERMD, r0)
  1612  
  1613  		case AVSEL: /* vsel */
  1614  			opset(AVSEL, r0)
  1615  
  1616  		case AVSPLTB: /* vspltb, vsplth, vspltw */
  1617  			opset(AVSPLTH, r0)
  1618  			opset(AVSPLTW, r0)
  1619  
  1620  		case AVSPLTISB: /* vspltisb, vspltish, vspltisw */
  1621  			opset(AVSPLTISH, r0)
  1622  			opset(AVSPLTISW, r0)
  1623  
  1624  		case AVCIPH: /* vcipher, vcipherlast */
  1625  			opset(AVCIPHER, r0)
  1626  			opset(AVCIPHERLAST, r0)
  1627  
  1628  		case AVNCIPH: /* vncipher, vncipherlast */
  1629  			opset(AVNCIPHER, r0)
  1630  			opset(AVNCIPHERLAST, r0)
  1631  
  1632  		case AVSBOX: /* vsbox */
  1633  			opset(AVSBOX, r0)
  1634  
  1635  		case AVSHASIGMA: /* vshasigmaw, vshasigmad */
  1636  			opset(AVSHASIGMAW, r0)
  1637  			opset(AVSHASIGMAD, r0)
  1638  
  1639  		case ALXVD2X: /* lxvd2x, lxvdsx, lxvw4x, lxvh8x, lxvb16x */
  1640  			opset(ALXVDSX, r0)
  1641  			opset(ALXVW4X, r0)
  1642  			opset(ALXVH8X, r0)
  1643  			opset(ALXVB16X, r0)
  1644  
  1645  		case ALXV: /* lxv */
  1646  			opset(ALXV, r0)
  1647  
  1648  		case ALXVL: /* lxvl, lxvll, lxvx */
  1649  			opset(ALXVLL, r0)
  1650  			opset(ALXVX, r0)
  1651  
  1652  		case ASTXVD2X: /* stxvd2x, stxvdsx, stxvw4x, stxvh8x, stxvb16x */
  1653  			opset(ASTXVW4X, r0)
  1654  			opset(ASTXVH8X, r0)
  1655  			opset(ASTXVB16X, r0)
  1656  
  1657  		case ASTXV: /* stxv */
  1658  			opset(ASTXV, r0)
  1659  
  1660  		case ASTXVL: /* stxvl, stxvll, stvx */
  1661  			opset(ASTXVLL, r0)
  1662  			opset(ASTXVX, r0)
  1663  
  1664  		case ALXSDX: /* lxsdx  */
  1665  			opset(ALXSDX, r0)
  1666  
  1667  		case ASTXSDX: /* stxsdx */
  1668  			opset(ASTXSDX, r0)
  1669  
  1670  		case ALXSIWAX: /* lxsiwax, lxsiwzx  */
  1671  			opset(ALXSIWZX, r0)
  1672  
  1673  		case ASTXSIWX: /* stxsiwx */
  1674  			opset(ASTXSIWX, r0)
  1675  
  1676  		case AMFVSRD: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */
  1677  			opset(AMFFPRD, r0)
  1678  			opset(AMFVRD, r0)
  1679  			opset(AMFVSRWZ, r0)
  1680  			opset(AMFVSRLD, r0)
  1681  
  1682  		case AMTVSRD: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */
  1683  			opset(AMTFPRD, r0)
  1684  			opset(AMTVRD, r0)
  1685  			opset(AMTVSRWA, r0)
  1686  			opset(AMTVSRWZ, r0)
  1687  			opset(AMTVSRWS, r0)
  1688  
  1689  		case AXXLAND:
  1690  			opset(AXXLANDC, r0)
  1691  			opset(AXXLEQV, r0)
  1692  			opset(AXXLNAND, r0)
  1693  			opset(AXXLORC, r0)
  1694  			opset(AXXLNOR, r0)
  1695  			opset(AXXLORQ, r0)
  1696  			opset(AXXLXOR, r0)
  1697  			opset(AXXLOR, r0)
  1698  			opset(AXSMAXJDP, r0)
  1699  			opset(AXSMINJDP, r0)
  1700  
  1701  		case AXXSEL: /* xxsel */
  1702  			opset(AXXSEL, r0)
  1703  
  1704  		case AXXMRGHW: /* xxmrghw, xxmrglw */
  1705  			opset(AXXMRGLW, r0)
  1706  
  1707  		case AXXSPLTW: /* xxspltw */
  1708  			opset(AXXSPLTW, r0)
  1709  
  1710  		case AXXSPLTIB: /* xxspltib */
  1711  			opset(AXXSPLTIB, r0)
  1712  
  1713  		case AXXPERM: /* xxpermdi */
  1714  			opset(AXXPERM, r0)
  1715  
  1716  		case AXXSLDWI: /* xxsldwi */
  1717  			opset(AXXPERMDI, r0)
  1718  			opset(AXXSLDWI, r0)
  1719  
  1720  		case AXXBRQ: /* xxbrq, xxbrd, xxbrw, xxbrh */
  1721  			opset(AXXBRD, r0)
  1722  			opset(AXXBRW, r0)
  1723  			opset(AXXBRH, r0)
  1724  
  1725  		case AXSCVDPSP: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */
  1726  			opset(AXSCVSPDP, r0)
  1727  			opset(AXSCVDPSPN, r0)
  1728  			opset(AXSCVSPDPN, r0)
  1729  
  1730  		case AXVCVDPSP: /* xvcvdpsp, xvcvspdp */
  1731  			opset(AXVCVSPDP, r0)
  1732  
  1733  		case AXSCVDPSXDS: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */
  1734  			opset(AXSCVDPSXWS, r0)
  1735  			opset(AXSCVDPUXDS, r0)
  1736  			opset(AXSCVDPUXWS, r0)
  1737  
  1738  		case AXSCVSXDDP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */
  1739  			opset(AXSCVUXDDP, r0)
  1740  			opset(AXSCVSXDSP, r0)
  1741  			opset(AXSCVUXDSP, r0)
  1742  
  1743  		case AXVCVDPSXDS: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */
  1744  			opset(AXVCVDPSXDS, r0)
  1745  			opset(AXVCVDPSXWS, r0)
  1746  			opset(AXVCVDPUXDS, r0)
  1747  			opset(AXVCVDPUXWS, r0)
  1748  			opset(AXVCVSPSXDS, r0)
  1749  			opset(AXVCVSPSXWS, r0)
  1750  			opset(AXVCVSPUXDS, r0)
  1751  			opset(AXVCVSPUXWS, r0)
  1752  
  1753  		case AXVCVSXDDP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */
  1754  			opset(AXVCVSXWDP, r0)
  1755  			opset(AXVCVUXDDP, r0)
  1756  			opset(AXVCVUXWDP, r0)
  1757  			opset(AXVCVSXDSP, r0)
  1758  			opset(AXVCVSXWSP, r0)
  1759  			opset(AXVCVUXDSP, r0)
  1760  			opset(AXVCVUXWSP, r0)
  1761  
  1762  		case AAND: /* logical op Rb,Rs,Ra; no literal */
  1763  			opset(AANDN, r0)
  1764  			opset(AANDNCC, r0)
  1765  			opset(AEQV, r0)
  1766  			opset(AEQVCC, r0)
  1767  			opset(ANAND, r0)
  1768  			opset(ANANDCC, r0)
  1769  			opset(ANOR, r0)
  1770  			opset(ANORCC, r0)
  1771  			opset(AORCC, r0)
  1772  			opset(AORN, r0)
  1773  			opset(AORNCC, r0)
  1774  			opset(AXORCC, r0)
  1775  
  1776  		case AADDME: /* op Ra, Rd */
  1777  			opset(AADDMECC, r0)
  1778  
  1779  			opset(AADDMEV, r0)
  1780  			opset(AADDMEVCC, r0)
  1781  			opset(AADDZE, r0)
  1782  			opset(AADDZECC, r0)
  1783  			opset(AADDZEV, r0)
  1784  			opset(AADDZEVCC, r0)
  1785  			opset(ASUBME, r0)
  1786  			opset(ASUBMECC, r0)
  1787  			opset(ASUBMEV, r0)
  1788  			opset(ASUBMEVCC, r0)
  1789  			opset(ASUBZE, r0)
  1790  			opset(ASUBZECC, r0)
  1791  			opset(ASUBZEV, r0)
  1792  			opset(ASUBZEVCC, r0)
  1793  
  1794  		case AADDC:
  1795  			opset(AADDCCC, r0)
  1796  
  1797  		case ABEQ:
  1798  			opset(ABGE, r0)
  1799  			opset(ABGT, r0)
  1800  			opset(ABLE, r0)
  1801  			opset(ABLT, r0)
  1802  			opset(ABNE, r0)
  1803  			opset(ABVC, r0)
  1804  			opset(ABVS, r0)
  1805  
  1806  		case ABR:
  1807  			opset(ABL, r0)
  1808  
  1809  		case ABC:
  1810  			opset(ABCL, r0)
  1811  
  1812  		case ABDNZ:
  1813  			opset(ABDZ, r0)
  1814  
  1815  		case AEXTSB: /* op Rs, Ra */
  1816  			opset(AEXTSBCC, r0)
  1817  
  1818  			opset(AEXTSH, r0)
  1819  			opset(AEXTSHCC, r0)
  1820  			opset(ACNTLZW, r0)
  1821  			opset(ACNTLZWCC, r0)
  1822  			opset(ACNTLZD, r0)
  1823  			opset(AEXTSW, r0)
  1824  			opset(AEXTSWCC, r0)
  1825  			opset(ACNTLZDCC, r0)
  1826  
  1827  		case AFABS: /* fop [s,]d */
  1828  			opset(AFABSCC, r0)
  1829  
  1830  			opset(AFNABS, r0)
  1831  			opset(AFNABSCC, r0)
  1832  			opset(AFNEG, r0)
  1833  			opset(AFNEGCC, r0)
  1834  			opset(AFRSP, r0)
  1835  			opset(AFRSPCC, r0)
  1836  			opset(AFCTIW, r0)
  1837  			opset(AFCTIWCC, r0)
  1838  			opset(AFCTIWZ, r0)
  1839  			opset(AFCTIWZCC, r0)
  1840  			opset(AFCTID, r0)
  1841  			opset(AFCTIDCC, r0)
  1842  			opset(AFCTIDZ, r0)
  1843  			opset(AFCTIDZCC, r0)
  1844  			opset(AFCFID, r0)
  1845  			opset(AFCFIDCC, r0)
  1846  			opset(AFCFIDU, r0)
  1847  			opset(AFCFIDUCC, r0)
  1848  			opset(AFCFIDS, r0)
  1849  			opset(AFCFIDSCC, r0)
  1850  			opset(AFRES, r0)
  1851  			opset(AFRESCC, r0)
  1852  			opset(AFRIM, r0)
  1853  			opset(AFRIMCC, r0)
  1854  			opset(AFRIP, r0)
  1855  			opset(AFRIPCC, r0)
  1856  			opset(AFRIZ, r0)
  1857  			opset(AFRIZCC, r0)
  1858  			opset(AFRIN, r0)
  1859  			opset(AFRINCC, r0)
  1860  			opset(AFRSQRTE, r0)
  1861  			opset(AFRSQRTECC, r0)
  1862  			opset(AFSQRT, r0)
  1863  			opset(AFSQRTCC, r0)
  1864  			opset(AFSQRTS, r0)
  1865  			opset(AFSQRTSCC, r0)
  1866  
  1867  		case AFADD:
  1868  			opset(AFADDS, r0)
  1869  			opset(AFADDCC, r0)
  1870  			opset(AFADDSCC, r0)
  1871  			opset(AFCPSGN, r0)
  1872  			opset(AFCPSGNCC, r0)
  1873  			opset(AFDIV, r0)
  1874  			opset(AFDIVS, r0)
  1875  			opset(AFDIVCC, r0)
  1876  			opset(AFDIVSCC, r0)
  1877  			opset(AFSUB, r0)
  1878  			opset(AFSUBS, r0)
  1879  			opset(AFSUBCC, r0)
  1880  			opset(AFSUBSCC, r0)
  1881  			opset(ADADD, r0)
  1882  			opset(ADDIV, r0)
  1883  			opset(ADSUB, r0)
  1884  
  1885  		case ADADDQ:
  1886  			opset(ADDIVQ, r0)
  1887  			opset(ADSUBQ, r0)
  1888  
  1889  		case AFMADD:
  1890  			opset(AFMADDCC, r0)
  1891  			opset(AFMADDS, r0)
  1892  			opset(AFMADDSCC, r0)
  1893  			opset(AFMSUB, r0)
  1894  			opset(AFMSUBCC, r0)
  1895  			opset(AFMSUBS, r0)
  1896  			opset(AFMSUBSCC, r0)
  1897  			opset(AFNMADD, r0)
  1898  			opset(AFNMADDCC, r0)
  1899  			opset(AFNMADDS, r0)
  1900  			opset(AFNMADDSCC, r0)
  1901  			opset(AFNMSUB, r0)
  1902  			opset(AFNMSUBCC, r0)
  1903  			opset(AFNMSUBS, r0)
  1904  			opset(AFNMSUBSCC, r0)
  1905  			opset(AFSEL, r0)
  1906  			opset(AFSELCC, r0)
  1907  
  1908  		case AFMUL:
  1909  			opset(AFMULS, r0)
  1910  			opset(AFMULCC, r0)
  1911  			opset(AFMULSCC, r0)
  1912  			opset(ADMUL, r0)
  1913  
  1914  		case ADMULQ:
  1915  			opset(ADMULQ, r0)
  1916  
  1917  		case AFCMPO:
  1918  			opset(AFCMPU, r0)
  1919  			opset(ADCMPU, r0)
  1920  			opset(ADCMPO, r0)
  1921  
  1922  		case ADCMPOQ:
  1923  			opset(ADCMPUQ, r0)
  1924  
  1925  		case AMTFSB0:
  1926  			opset(AMTFSB0CC, r0)
  1927  			opset(AMTFSB1, r0)
  1928  			opset(AMTFSB1CC, r0)
  1929  
  1930  		case ANEG: /* op [Ra,] Rd */
  1931  			opset(ANEGCC, r0)
  1932  
  1933  			opset(ANEGV, r0)
  1934  			opset(ANEGVCC, r0)
  1935  
  1936  		case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,R */
  1937  			opset(AXOR, r0)
  1938  
  1939  		case AORIS: /* oris/xoris $uimm,Rs,Ra */
  1940  			opset(AXORIS, r0)
  1941  
  1942  		case ASLW:
  1943  			opset(ASLWCC, r0)
  1944  			opset(ASRW, r0)
  1945  			opset(ASRWCC, r0)
  1946  			opset(AROTLW, r0)
  1947  
  1948  		case ASLD:
  1949  			opset(ASLDCC, r0)
  1950  			opset(ASRD, r0)
  1951  			opset(ASRDCC, r0)
  1952  			opset(AROTL, r0)
  1953  
  1954  		case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
  1955  			opset(ASRAWCC, r0)
  1956  
  1957  		case AEXTSWSLI:
  1958  			opset(AEXTSWSLICC, r0)
  1959  
  1960  		case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
  1961  			opset(ASRADCC, r0)
  1962  
  1963  		case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */
  1964  			opset(ASUB, r0)
  1965  
  1966  			opset(ASUBCC, r0)
  1967  			opset(ASUBV, r0)
  1968  			opset(ASUBVCC, r0)
  1969  			opset(ASUBCCC, r0)
  1970  			opset(ASUBCV, r0)
  1971  			opset(ASUBCVCC, r0)
  1972  			opset(ASUBE, r0)
  1973  			opset(ASUBECC, r0)
  1974  			opset(ASUBEV, r0)
  1975  			opset(ASUBEVCC, r0)
  1976  
  1977  		case ASYNC:
  1978  			opset(AISYNC, r0)
  1979  			opset(ALWSYNC, r0)
  1980  			opset(APTESYNC, r0)
  1981  			opset(ATLBSYNC, r0)
  1982  
  1983  		case ARLWNM:
  1984  			opset(ARLWNMCC, r0)
  1985  			opset(ARLWMI, r0)
  1986  			opset(ARLWMICC, r0)
  1987  
  1988  		case ARLDMI:
  1989  			opset(ARLDMICC, r0)
  1990  			opset(ARLDIMI, r0)
  1991  			opset(ARLDIMICC, r0)
  1992  
  1993  		case ARLDC:
  1994  			opset(ARLDCCC, r0)
  1995  
  1996  		case ARLDCL:
  1997  			opset(ARLDCR, r0)
  1998  			opset(ARLDCLCC, r0)
  1999  			opset(ARLDCRCC, r0)
  2000  
  2001  		case ARLDICL:
  2002  			opset(ARLDICLCC, r0)
  2003  			opset(ARLDICR, r0)
  2004  			opset(ARLDICRCC, r0)
  2005  			opset(ARLDIC, r0)
  2006  			opset(ARLDICCC, r0)
  2007  			opset(ACLRLSLDI, r0)
  2008  
  2009  		case AFMOVD:
  2010  			opset(AFMOVDCC, r0)
  2011  			opset(AFMOVDU, r0)
  2012  			opset(AFMOVS, r0)
  2013  			opset(AFMOVSU, r0)
  2014  
  2015  		case ALDAR:
  2016  			opset(ALBAR, r0)
  2017  			opset(ALHAR, r0)
  2018  			opset(ALWAR, r0)
  2019  
  2020  		case ASYSCALL: /* just the op; flow of control */
  2021  			opset(ARFI, r0)
  2022  
  2023  			opset(ARFCI, r0)
  2024  			opset(ARFID, r0)
  2025  			opset(AHRFID, r0)
  2026  
  2027  		case AMOVHBR:
  2028  			opset(AMOVWBR, r0)
  2029  			opset(AMOVDBR, r0)
  2030  
  2031  		case ASLBMFEE:
  2032  			opset(ASLBMFEV, r0)
  2033  
  2034  		case ATW:
  2035  			opset(ATD, r0)
  2036  
  2037  		case ATLBIE:
  2038  			opset(ASLBIE, r0)
  2039  			opset(ATLBIEL, r0)
  2040  
  2041  		case AEIEIO:
  2042  			opset(ASLBIA, r0)
  2043  
  2044  		case ACMP:
  2045  			opset(ACMPW, r0)
  2046  
  2047  		case ACMPU:
  2048  			opset(ACMPWU, r0)
  2049  
  2050  		case ACMPB:
  2051  			opset(ACMPB, r0)
  2052  
  2053  		case AFTDIV:
  2054  			opset(AFTDIV, r0)
  2055  
  2056  		case AFTSQRT:
  2057  			opset(AFTSQRT, r0)
  2058  
  2059  		case AMOVW: /* load/store/move word with sign extension; move 32-bit literals  */
  2060  			opset(AMOVWZ, r0) /* Same as above, but zero extended */
  2061  
  2062  		case AVCLZLSBB:
  2063  			opset(AVCTZLSBB, r0)
  2064  
  2065  		case AADD,
  2066  			AADDIS,
  2067  			AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra */
  2068  			AANDISCC,
  2069  			AFMOVSX,
  2070  			AFMOVSZ,
  2071  			ALSW,
  2072  			AMOVD,  /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */
  2073  			AMOVB,  /* macro: move byte with sign extension */
  2074  			AMOVBU, /* macro: move byte with sign extension & update */
  2075  			AMOVFL,
  2076  			/* op $s[,r2],r3; op r1[,r2],r3; no cc/v */
  2077  			ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */
  2078  			ASTSW,
  2079  			ASLBMTE,
  2080  			AWORD,
  2081  			ADWORD,
  2082  			ADARN,
  2083  			AVMSUMUDM,
  2084  			AADDEX,
  2085  			ACMPEQB,
  2086  			ACLRLSLWI,
  2087  			AMTVSRDD,
  2088  			APNOP,
  2089  			AISEL,
  2090  			ASETB,
  2091  			obj.ANOP,
  2092  			obj.ATEXT,
  2093  			obj.AUNDEF,
  2094  			obj.AFUNCDATA,
  2095  			obj.APCALIGN,
  2096  			obj.APCDATA,
  2097  			obj.ADUFFZERO,
  2098  			obj.ADUFFCOPY:
  2099  			break
  2100  		}
  2101  	}
  2102  }
  2103  
  2104  func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
  2105  	return o<<26 | xo<<1 | oe<<11
  2106  }
  2107  
  2108  func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
  2109  	return o<<26 | xo<<2 | oe<<11
  2110  }
  2111  
  2112  func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32 {
  2113  	return o<<26 | xo<<2 | oe<<16
  2114  }
  2115  
  2116  func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
  2117  	return o<<26 | xo<<3 | oe<<11
  2118  }
  2119  
  2120  func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
  2121  	return o<<26 | xo<<4 | oe<<11
  2122  }
  2123  
  2124  func OPDQ(o uint32, xo uint32, oe uint32) uint32 {
  2125  	return o<<26 | xo | oe<<4
  2126  }
  2127  
  2128  func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  2129  	return o<<26 | xo | oe<<11 | rc&1
  2130  }
  2131  
  2132  func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  2133  	return o<<26 | xo | oe<<11 | (rc&1)<<10
  2134  }
  2135  
  2136  func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  2137  	return o<<26 | xo<<1 | oe<<10 | rc&1
  2138  }
  2139  
  2140  func OPCC(o uint32, xo uint32, rc uint32) uint32 {
  2141  	return OPVCC(o, xo, 0, rc)
  2142  }
  2143  
  2144  /* Generate MD-form opcode */
  2145  func OPMD(o, xo, rc uint32) uint32 {
  2146  	return o<<26 | xo<<2 | rc&1
  2147  }
  2148  
  2149  /* the order is dest, a/s, b/imm for both arithmetic and logical operations. */
  2150  func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
  2151  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
  2152  }
  2153  
  2154  /* VX-form 2-register operands, r/none/r */
  2155  func AOP_RR(op uint32, d uint32, a uint32) uint32 {
  2156  	return op | (d&31)<<21 | (a&31)<<11
  2157  }
  2158  
  2159  /* VA-form 4-register operands */
  2160  func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2161  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
  2162  }
  2163  
  2164  func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
  2165  	return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
  2166  }
  2167  
  2168  /* VX-form 2-register + UIM operands */
  2169  func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
  2170  	return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
  2171  }
  2172  
  2173  /* VX-form 2-register + ST + SIX operands */
  2174  func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
  2175  	return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
  2176  }
  2177  
  2178  /* VA-form 3-register + SHB operands */
  2179  func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
  2180  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
  2181  }
  2182  
  2183  /* VX-form 1-register + SIM operands */
  2184  func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
  2185  	return op | (d&31)<<21 | (simm&31)<<16
  2186  }
  2187  
  2188  /* XX1-form 3-register operands, 1 VSR operand */
  2189  func AOP_XX1(op uint32, r uint32, a uint32, b uint32) uint32 {
  2190  	return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
  2191  }
  2192  
  2193  /* XX2-form 3-register operands, 2 VSR operands */
  2194  func AOP_XX2(op uint32, xt uint32, a uint32, xb uint32) uint32 {
  2195  	return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
  2196  }
  2197  
  2198  /* XX3-form 3 VSR operands */
  2199  func AOP_XX3(op uint32, xt uint32, xa uint32, xb uint32) uint32 {
  2200  	return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2201  }
  2202  
  2203  /* XX3-form 3 VSR operands + immediate */
  2204  func AOP_XX3I(op uint32, xt uint32, xa uint32, xb uint32, c uint32) uint32 {
  2205  	return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2206  }
  2207  
  2208  /* XX4-form, 4 VSR operands */
  2209  func AOP_XX4(op uint32, xt uint32, xa uint32, xb uint32, xc uint32) uint32 {
  2210  	return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2211  }
  2212  
  2213  /* DQ-form, VSR register, register + offset operands */
  2214  func AOP_DQ(op uint32, xt uint32, a uint32, b uint32) uint32 {
  2215  	/* The EA for this instruction form is (RA) + DQ << 4, where DQ is a 12-bit signed integer. */
  2216  	/* In order to match the output of the GNU objdump (and make the usage in Go asm easier), the */
  2217  	/* instruction is called using the sign extended value (i.e. a valid offset would be -32752 or 32752, */
  2218  	/* not -2047 or 2047), so 'b' needs to be adjusted to the expected 12-bit DQ value. Bear in mind that */
  2219  	/* bits 0 to 3 in 'dq' need to be zero, otherwise this will generate an illegal instruction. */
  2220  	/* If in doubt how this instruction form is encoded, refer to ISA 3.0b, pages 492 and 507. */
  2221  	dq := b >> 4
  2222  	return op | (xt&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (xt&32)>>2
  2223  }
  2224  
  2225  /* Z23-form, 3-register operands + CY field */
  2226  func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2227  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<9
  2228  }
  2229  
  2230  /* X-form, 3-register operands + EH field */
  2231  func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2232  	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
  2233  }
  2234  
  2235  func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
  2236  	return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
  2237  }
  2238  
  2239  func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
  2240  	return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
  2241  }
  2242  
  2243  func OP_BR(op uint32, li uint32, aa uint32) uint32 {
  2244  	return op | li&0x03FFFFFC | aa<<1
  2245  }
  2246  
  2247  func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
  2248  	return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
  2249  }
  2250  
  2251  func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
  2252  	return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
  2253  }
  2254  
  2255  func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
  2256  	return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
  2257  }
  2258  
  2259  func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32 {
  2260  	return op | (a&31)<<21 | (s&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1
  2261  }
  2262  
  2263  func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
  2264  	return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
  2265  }
  2266  
  2267  /* MD-form 2-register, 2 6-bit immediate operands */
  2268  func AOP_MD(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
  2269  	return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
  2270  }
  2271  
  2272  /* MDS-form 3-register, 1 6-bit immediate operands. rsh argument is a register. */
  2273  func AOP_MDS(op, to, from, rsh, m uint32) uint32 {
  2274  	return AOP_MD(op, to, from, rsh&31, m)
  2275  }
  2276  
  2277  func AOP_PFX_00_8LS(r, ie uint32) uint32 {
  2278  	return 1<<26 | 0<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
  2279  }
  2280  func AOP_PFX_10_MLS(r, ie uint32) uint32 {
  2281  	return 1<<26 | 2<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
  2282  }
  2283  
  2284  const (
  2285  	/* each rhs is OPVCC(_, _, _, _) */
  2286  	OP_ADD      = 31<<26 | 266<<1 | 0<<10 | 0
  2287  	OP_ADDI     = 14<<26 | 0<<1 | 0<<10 | 0
  2288  	OP_ADDIS    = 15<<26 | 0<<1 | 0<<10 | 0
  2289  	OP_ANDI     = 28<<26 | 0<<1 | 0<<10 | 0
  2290  	OP_EXTSB    = 31<<26 | 954<<1 | 0<<10 | 0
  2291  	OP_EXTSH    = 31<<26 | 922<<1 | 0<<10 | 0
  2292  	OP_EXTSW    = 31<<26 | 986<<1 | 0<<10 | 0
  2293  	OP_ISEL     = 31<<26 | 15<<1 | 0<<10 | 0
  2294  	OP_MCRF     = 19<<26 | 0<<1 | 0<<10 | 0
  2295  	OP_MCRFS    = 63<<26 | 64<<1 | 0<<10 | 0
  2296  	OP_MCRXR    = 31<<26 | 512<<1 | 0<<10 | 0
  2297  	OP_MFCR     = 31<<26 | 19<<1 | 0<<10 | 0
  2298  	OP_MFFS     = 63<<26 | 583<<1 | 0<<10 | 0
  2299  	OP_MFSPR    = 31<<26 | 339<<1 | 0<<10 | 0
  2300  	OP_MFSR     = 31<<26 | 595<<1 | 0<<10 | 0
  2301  	OP_MFSRIN   = 31<<26 | 659<<1 | 0<<10 | 0
  2302  	OP_MTCRF    = 31<<26 | 144<<1 | 0<<10 | 0
  2303  	OP_MTFSF    = 63<<26 | 711<<1 | 0<<10 | 0
  2304  	OP_MTFSFI   = 63<<26 | 134<<1 | 0<<10 | 0
  2305  	OP_MTSPR    = 31<<26 | 467<<1 | 0<<10 | 0
  2306  	OP_MTSR     = 31<<26 | 210<<1 | 0<<10 | 0
  2307  	OP_MTSRIN   = 31<<26 | 242<<1 | 0<<10 | 0
  2308  	OP_MULLW    = 31<<26 | 235<<1 | 0<<10 | 0
  2309  	OP_MULLD    = 31<<26 | 233<<1 | 0<<10 | 0
  2310  	OP_OR       = 31<<26 | 444<<1 | 0<<10 | 0
  2311  	OP_ORI      = 24<<26 | 0<<1 | 0<<10 | 0
  2312  	OP_ORIS     = 25<<26 | 0<<1 | 0<<10 | 0
  2313  	OP_XORI     = 26<<26 | 0<<1 | 0<<10 | 0
  2314  	OP_XORIS    = 27<<26 | 0<<1 | 0<<10 | 0
  2315  	OP_RLWINM   = 21<<26 | 0<<1 | 0<<10 | 0
  2316  	OP_RLWNM    = 23<<26 | 0<<1 | 0<<10 | 0
  2317  	OP_SUBF     = 31<<26 | 40<<1 | 0<<10 | 0
  2318  	OP_RLDIC    = 30<<26 | 4<<1 | 0<<10 | 0
  2319  	OP_RLDICR   = 30<<26 | 2<<1 | 0<<10 | 0
  2320  	OP_RLDICL   = 30<<26 | 0<<1 | 0<<10 | 0
  2321  	OP_RLDCL    = 30<<26 | 8<<1 | 0<<10 | 0
  2322  	OP_EXTSWSLI = 31<<26 | 445<<2
  2323  	OP_SETB     = 31<<26 | 128<<1
  2324  )
  2325  
  2326  func pfxadd(rt, ra int16, r uint32, imm32 int64) (uint32, uint32) {
  2327  	return AOP_PFX_10_MLS(r, uint32(imm32>>16)), AOP_IRR(14<<26, uint32(rt), uint32(ra), uint32(imm32))
  2328  }
  2329  
  2330  func pfxload(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
  2331  	switch a {
  2332  	case AMOVH:
  2333  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(42<<26, uint32(reg), uint32(base), 0)
  2334  	case AMOVW:
  2335  		return AOP_PFX_00_8LS(r, 0), AOP_IRR(41<<26, uint32(reg), uint32(base), 0)
  2336  	case AMOVD:
  2337  		return AOP_PFX_00_8LS(r, 0), AOP_IRR(57<<26, uint32(reg), uint32(base), 0)
  2338  	case AMOVBZ, AMOVB:
  2339  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(34<<26, uint32(reg), uint32(base), 0)
  2340  	case AMOVHZ:
  2341  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(40<<26, uint32(reg), uint32(base), 0)
  2342  	case AMOVWZ:
  2343  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(32<<26, uint32(reg), uint32(base), 0)
  2344  	case AFMOVS:
  2345  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(48<<26, uint32(reg), uint32(base), 0)
  2346  	case AFMOVD:
  2347  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(50<<26, uint32(reg), uint32(base), 0)
  2348  	}
  2349  	log.Fatalf("Error no pfxload for %v\n", a)
  2350  	return 0, 0
  2351  }
  2352  
  2353  func pfxstore(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
  2354  	switch a {
  2355  	case AMOVD:
  2356  		return AOP_PFX_00_8LS(r, 0), AOP_IRR(61<<26, uint32(reg), uint32(base), 0)
  2357  	case AMOVBZ, AMOVB:
  2358  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(38<<26, uint32(reg), uint32(base), 0)
  2359  	case AMOVHZ, AMOVH:
  2360  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(44<<26, uint32(reg), uint32(base), 0)
  2361  	case AMOVWZ, AMOVW:
  2362  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(36<<26, uint32(reg), uint32(base), 0)
  2363  	case AFMOVS:
  2364  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(52<<26, uint32(reg), uint32(base), 0)
  2365  	case AFMOVD:
  2366  		return AOP_PFX_10_MLS(r, 0), AOP_IRR(54<<26, uint32(reg), uint32(base), 0)
  2367  	}
  2368  	log.Fatalf("Error no pfxstore for %v\n", a)
  2369  	return 0, 0
  2370  }
  2371  
  2372  func oclass(a *obj.Addr) int {
  2373  	return int(a.Class) - 1
  2374  }
  2375  
  2376  const (
  2377  	D_FORM = iota
  2378  	DS_FORM
  2379  )
  2380  
  2381  // This function determines when a non-indexed load or store is D or
  2382  // DS form for use in finding the size of the offset field in the instruction.
  2383  // The size is needed when setting the offset value in the instruction
  2384  // and when generating relocation for that field.
  2385  // DS form instructions include: ld, ldu, lwa, std, stdu.  All other
  2386  // loads and stores with an offset field are D form.  This function should
  2387  // only be called with the same opcodes as are handled by opstore and opload.
  2388  func (c *ctxt9) opform(insn uint32) int {
  2389  	switch insn {
  2390  	default:
  2391  		c.ctxt.Diag("bad insn in loadform: %x", insn)
  2392  	case OPVCC(58, 0, 0, 0), // ld
  2393  		OPVCC(58, 0, 0, 1),        // ldu
  2394  		OPVCC(58, 0, 0, 0) | 1<<1, // lwa
  2395  		OPVCC(62, 0, 0, 0),        // std
  2396  		OPVCC(62, 0, 0, 1):        //stdu
  2397  		return DS_FORM
  2398  	case OP_ADDI, // add
  2399  		OPVCC(32, 0, 0, 0), // lwz
  2400  		OPVCC(33, 0, 0, 0), // lwzu
  2401  		OPVCC(34, 0, 0, 0), // lbz
  2402  		OPVCC(35, 0, 0, 0), // lbzu
  2403  		OPVCC(40, 0, 0, 0), // lhz
  2404  		OPVCC(41, 0, 0, 0), // lhzu
  2405  		OPVCC(42, 0, 0, 0), // lha
  2406  		OPVCC(43, 0, 0, 0), // lhau
  2407  		OPVCC(46, 0, 0, 0), // lmw
  2408  		OPVCC(48, 0, 0, 0), // lfs
  2409  		OPVCC(49, 0, 0, 0), // lfsu
  2410  		OPVCC(50, 0, 0, 0), // lfd
  2411  		OPVCC(51, 0, 0, 0), // lfdu
  2412  		OPVCC(36, 0, 0, 0), // stw
  2413  		OPVCC(37, 0, 0, 0), // stwu
  2414  		OPVCC(38, 0, 0, 0), // stb
  2415  		OPVCC(39, 0, 0, 0), // stbu
  2416  		OPVCC(44, 0, 0, 0), // sth
  2417  		OPVCC(45, 0, 0, 0), // sthu
  2418  		OPVCC(47, 0, 0, 0), // stmw
  2419  		OPVCC(52, 0, 0, 0), // stfs
  2420  		OPVCC(53, 0, 0, 0), // stfsu
  2421  		OPVCC(54, 0, 0, 0), // stfd
  2422  		OPVCC(55, 0, 0, 0): // stfdu
  2423  		return D_FORM
  2424  	}
  2425  	return 0
  2426  }
  2427  
  2428  // Encode instructions and create relocation for accessing s+d according to the
  2429  // instruction op with source or destination (as appropriate) register reg.
  2430  // The caller must call c.cursym.AddRel(c.ctxt, rel) when finished editing rel.
  2431  func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32, reuse bool) (o1, o2 uint32, rel obj.Reloc) {
  2432  	if c.ctxt.Headtype == objabi.Haix {
  2433  		// Every symbol access must be made via a TOC anchor.
  2434  		c.ctxt.Diag("symbolAccess called for %s", s.Name)
  2435  	}
  2436  	var base uint32
  2437  	form := c.opform(op)
  2438  	if c.ctxt.Flag_shared {
  2439  		base = REG_R2
  2440  	} else {
  2441  		base = REG_R0
  2442  	}
  2443  	// If reg can be reused when computing the symbol address,
  2444  	// use it instead of REGTMP.
  2445  	if !reuse {
  2446  		o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
  2447  		o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
  2448  	} else {
  2449  		o1 = AOP_IRR(OP_ADDIS, uint32(reg), base, 0)
  2450  		o2 = AOP_IRR(op, uint32(reg), uint32(reg), 0)
  2451  	}
  2452  	var typ objabi.RelocType
  2453  	if c.ctxt.Flag_shared {
  2454  		switch form {
  2455  		case D_FORM:
  2456  			typ = objabi.R_ADDRPOWER_TOCREL
  2457  		case DS_FORM:
  2458  			typ = objabi.R_ADDRPOWER_TOCREL_DS
  2459  		}
  2460  	} else {
  2461  		switch form {
  2462  		case D_FORM:
  2463  			typ = objabi.R_ADDRPOWER
  2464  		case DS_FORM:
  2465  			typ = objabi.R_ADDRPOWER_DS
  2466  		}
  2467  	}
  2468  	rel = obj.Reloc{
  2469  		Type: typ,
  2470  		Off:  int32(c.pc),
  2471  		Siz:  8,
  2472  		Sym:  s,
  2473  		Add:  d,
  2474  	}
  2475  	return
  2476  }
  2477  
  2478  // Determine the mask begin (mb) and mask end (me) values
  2479  // for a valid word rotate mask. A valid 32 bit mask is of
  2480  // the form 1+0*1+ or 0*1+0*.
  2481  //
  2482  // Note, me is inclusive.
  2483  func decodeMask32(mask uint32) (mb, me uint32, valid bool) {
  2484  	mb = uint32(bits.LeadingZeros32(mask))
  2485  	me = uint32(32 - bits.TrailingZeros32(mask))
  2486  	mbn := uint32(bits.LeadingZeros32(^mask))
  2487  	men := uint32(32 - bits.TrailingZeros32(^mask))
  2488  	// Check for a wrapping mask (e.g bits at 0 and 31)
  2489  	if mb == 0 && me == 32 {
  2490  		// swap the inverted values
  2491  		mb, me = men, mbn
  2492  	}
  2493  
  2494  	// Validate mask is of the binary form 1+0*1+ or 0*1+0*
  2495  	// Isolate rightmost 1 (if none 0) and add.
  2496  	v := mask
  2497  	vp := (v & -v) + v
  2498  	// Likewise, check for the wrapping (inverted) case.
  2499  	vn := ^v
  2500  	vpn := (vn & -vn) + vn
  2501  	return mb, (me - 1) & 31, (v&vp == 0 || vn&vpn == 0) && v != 0
  2502  }
  2503  
  2504  // Decompose a mask of contiguous bits into a begin (mb) and
  2505  // end (me) value.
  2506  //
  2507  // 64b mask values cannot wrap on any valid PPC64 instruction.
  2508  // Only masks of the form 0*1+0* are valid.
  2509  //
  2510  // Note, me is inclusive.
  2511  func decodeMask64(mask int64) (mb, me uint32, valid bool) {
  2512  	m := uint64(mask)
  2513  	mb = uint32(bits.LeadingZeros64(m))
  2514  	me = uint32(64 - bits.TrailingZeros64(m))
  2515  	valid = ((m&-m)+m)&m == 0 && m != 0
  2516  	return mb, (me - 1) & 63, valid
  2517  }
  2518  
  2519  // Load the lower 16 bits of a constant into register r.
  2520  func loadl16(r int, d int64) uint32 {
  2521  	v := uint16(d)
  2522  	if v == 0 {
  2523  		// Avoid generating "ori r,r,0", r != 0. Instead, generate the architecturally preferred nop.
  2524  		// For example, "ori r31,r31,0" is a special execution serializing nop on Power10 called "exser".
  2525  		return NOP
  2526  	}
  2527  	return LOP_IRR(OP_ORI, uint32(r), uint32(r), uint32(v))
  2528  }
  2529  
  2530  // Load the upper 16 bits of a 32b constant into register r.
  2531  func loadu32(r int, d int64) uint32 {
  2532  	v := int32(d >> 16)
  2533  	if isuint32(uint64(d)) {
  2534  		return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
  2535  	}
  2536  	return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
  2537  }
  2538  
  2539  func high16adjusted(d int32) uint16 {
  2540  	if d&0x8000 != 0 {
  2541  		return uint16((d >> 16) + 1)
  2542  	}
  2543  	return uint16(d >> 16)
  2544  }
  2545  
  2546  func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
  2547  	o1 := uint32(0)
  2548  	o2 := uint32(0)
  2549  	o3 := uint32(0)
  2550  	o4 := uint32(0)
  2551  	o5 := uint32(0)
  2552  
  2553  	//print("%v => case %d\n", p, o->type);
  2554  	switch o.type_ {
  2555  	default:
  2556  		c.ctxt.Diag("unknown type %d", o.type_)
  2557  		prasm(p)
  2558  
  2559  	case 0: /* pseudo ops */
  2560  		break
  2561  
  2562  	case 2: /* int/cr/fp op Rb,[Ra],Rd */
  2563  		r := int(p.Reg)
  2564  
  2565  		if r == 0 {
  2566  			r = int(p.To.Reg)
  2567  		}
  2568  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
  2569  
  2570  	case 3: /* mov $soreg/16con, r ==> addi/ori $i,reg',r */
  2571  		d := c.vregoff(&p.From)
  2572  
  2573  		v := int32(d)
  2574  		r := int(p.From.Reg)
  2575  
  2576  		if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) {
  2577  			c.ctxt.Diag("literal operation on R0\n%v", p)
  2578  		}
  2579  		if int64(int16(d)) == d {
  2580  			// MOVD $int16, Ry  or  MOVD $offset(Rx), Ry
  2581  			o1 = AOP_IRR(uint32(OP_ADDI), uint32(p.To.Reg), uint32(r), uint32(v))
  2582  		} else {
  2583  			// MOVD $uint16, Ry
  2584  			if int64(uint16(d)) != d || (r != 0 && r != REGZERO) {
  2585  				c.ctxt.Diag("Rule expects a uint16 constant load. got:\n%v", p)
  2586  			}
  2587  			o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
  2588  		}
  2589  
  2590  	case 4: /* add/mul $scon,[r1],r2 */
  2591  		v := c.regoff(&p.From)
  2592  
  2593  		r := int(p.Reg)
  2594  		if r == 0 {
  2595  			r = int(p.To.Reg)
  2596  		}
  2597  		if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 {
  2598  			c.ctxt.Diag("literal operation on R0\n%v", p)
  2599  		}
  2600  		if int32(int16(v)) != v {
  2601  			log.Fatalf("mishandled instruction %v", p)
  2602  		}
  2603  		o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  2604  
  2605  	case 5: /* syscall */
  2606  		o1 = c.oprrr(p.As)
  2607  
  2608  	case 6: /* logical op Rb,[Rs,]Ra; no literal */
  2609  		r := int(p.Reg)
  2610  
  2611  		if r == 0 {
  2612  			r = int(p.To.Reg)
  2613  		}
  2614  		// AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM.
  2615  		switch p.As {
  2616  		case AROTL:
  2617  			o1 = AOP_MD(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
  2618  		case AROTLW:
  2619  			o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
  2620  		default:
  2621  			if p.As == AOR && p.From.Type == obj.TYPE_CONST && p.From.Offset == 0 {
  2622  				// Compile "OR $0, Rx, Ry" into ori. If Rx == Ry == 0, this is the preferred
  2623  				// hardware no-op. This happens because $0 matches C_REG before C_ZCON.
  2624  				o1 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(r), 0)
  2625  			} else {
  2626  				o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
  2627  			}
  2628  		}
  2629  
  2630  	case 7: /* mov r, soreg ==> stw o(r) */
  2631  		r := int(p.To.Reg)
  2632  		v := c.regoff(&p.To)
  2633  		if int32(int16(v)) != v {
  2634  			log.Fatalf("mishandled instruction %v", p)
  2635  		}
  2636  		// Offsets in DS form stores must be a multiple of 4
  2637  		inst := c.opstore(p.As)
  2638  		if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  2639  			log.Fatalf("invalid offset for DS form load/store %v", p)
  2640  		}
  2641  		o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
  2642  
  2643  	case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r), lbz o(r) + extsb r,r */
  2644  		r := int(p.From.Reg)
  2645  		v := c.regoff(&p.From)
  2646  		if int32(int16(v)) != v {
  2647  			log.Fatalf("mishandled instruction %v", p)
  2648  		}
  2649  		// Offsets in DS form loads must be a multiple of 4
  2650  		inst := c.opload(p.As)
  2651  		if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  2652  			log.Fatalf("invalid offset for DS form load/store %v", p)
  2653  		}
  2654  		o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
  2655  
  2656  		// Sign extend MOVB operations. This is ignored for other cases (o.size == 4).
  2657  		o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  2658  
  2659  	case 9: /* RLDC Ra, $sh, $mb, Rb */
  2660  		sh := uint32(p.RestArgs[0].Addr.Offset) & 0x3F
  2661  		mb := uint32(p.RestArgs[1].Addr.Offset) & 0x3F
  2662  		o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), (uint32(sh) & 0x1F))
  2663  		o1 |= (sh & 0x20) >> 4 // sh[5] is placed in bit 1.
  2664  		o1 |= (mb & 0x1F) << 6 // mb[0:4] is placed in bits 6-10.
  2665  		o1 |= (mb & 0x20)      // mb[5] is placed in bit 5
  2666  
  2667  	case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */
  2668  		r := int(p.Reg)
  2669  
  2670  		if r == 0 {
  2671  			r = int(p.To.Reg)
  2672  		}
  2673  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
  2674  
  2675  	case 11: /* br/bl bra */
  2676  		v := int32(0)
  2677  
  2678  		if p.To.Target() != nil {
  2679  			v = int32(p.To.Target().Pc - p.Pc)
  2680  			if v&03 != 0 {
  2681  				c.ctxt.Diag("odd branch target address\n%v", p)
  2682  				v &^= 03
  2683  			}
  2684  
  2685  			if v < -(1<<25) || v >= 1<<24 {
  2686  				c.ctxt.Diag("branch too far\n%v", p)
  2687  			}
  2688  		}
  2689  
  2690  		o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
  2691  		if p.To.Sym != nil {
  2692  			v += int32(p.To.Offset)
  2693  			if v&03 != 0 {
  2694  				c.ctxt.Diag("odd branch target address\n%v", p)
  2695  				v &^= 03
  2696  			}
  2697  			c.cursym.AddRel(c.ctxt, obj.Reloc{
  2698  				Type: objabi.R_CALLPOWER,
  2699  				Off:  int32(c.pc),
  2700  				Siz:  4,
  2701  				Sym:  p.To.Sym,
  2702  				Add:  int64(v),
  2703  			})
  2704  		}
  2705  		o2 = NOP // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking
  2706  
  2707  	case 13: /* mov[bhwd]{z,} r,r */
  2708  		// This needs to handle "MOV* $0, Rx".  This shows up because $0 also
  2709  		// matches C_REG if r0iszero. This happens because C_REG sorts before C_U16CON
  2710  		// TODO: fix the above behavior and cleanup this exception.
  2711  		if p.From.Type == obj.TYPE_CONST {
  2712  			o1 = LOP_IRR(OP_ADDI, REGZERO, uint32(p.To.Reg), 0)
  2713  			break
  2714  		}
  2715  		if p.To.Type == obj.TYPE_CONST {
  2716  			c.ctxt.Diag("cannot move into constant 0\n%v", p)
  2717  		}
  2718  
  2719  		switch p.As {
  2720  		case AMOVB:
  2721  			o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2722  		case AMOVBZ:
  2723  			o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
  2724  		case AMOVH:
  2725  			o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2726  		case AMOVHZ:
  2727  			o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
  2728  		case AMOVW:
  2729  			o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2730  		case AMOVWZ:
  2731  			o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */
  2732  		case AMOVD:
  2733  			o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
  2734  		default:
  2735  			c.ctxt.Diag("internal: bad register move/truncation\n%v", p)
  2736  		}
  2737  
  2738  	case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */
  2739  		r := uint32(p.Reg)
  2740  
  2741  		if r == 0 {
  2742  			r = uint32(p.To.Reg)
  2743  		}
  2744  		d := c.vregoff(p.GetFrom3())
  2745  		switch p.As {
  2746  
  2747  		// These opcodes expect a mask operand that has to be converted into the
  2748  		// appropriate operand.  The way these were defined, not all valid masks are possible.
  2749  		// Left here for compatibility in case they were used or generated.
  2750  		case ARLDCL, ARLDCLCC:
  2751  			mb, me, valid := decodeMask64(d)
  2752  			if me != 63 || !valid {
  2753  				c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
  2754  			}
  2755  			o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), mb)
  2756  
  2757  		case ARLDCR, ARLDCRCC:
  2758  			mb, me, valid := decodeMask64(d)
  2759  			if mb != 0 || !valid {
  2760  				c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p)
  2761  			}
  2762  			o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), me)
  2763  
  2764  		// These opcodes use a shift count like the ppc64 asm, no mask conversion done
  2765  		case ARLDICR, ARLDICRCC:
  2766  			me := uint32(d)
  2767  			sh := c.regoff(&p.From)
  2768  			if me < 0 || me > 63 || sh > 63 {
  2769  				c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh, p)
  2770  			}
  2771  			o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), me)
  2772  
  2773  		case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
  2774  			mb := uint32(d)
  2775  			sh := c.regoff(&p.From)
  2776  			if mb < 0 || mb > 63 || sh > 63 {
  2777  				c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh, p)
  2778  			}
  2779  			o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), mb)
  2780  
  2781  		case ACLRLSLDI:
  2782  			// This is an extended mnemonic defined in the ISA section C.8.1
  2783  			// clrlsldi ra,rs,b,n --> rldic ra,rs,n,b-n
  2784  			// It maps onto RLDIC so is directly generated here based on the operands from
  2785  			// the clrlsldi.
  2786  			n := int32(d)
  2787  			b := c.regoff(&p.From)
  2788  			if n > b || b > 63 {
  2789  				c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b, p)
  2790  			}
  2791  			o1 = AOP_MD(OP_RLDIC, uint32(p.To.Reg), uint32(r), uint32(n), uint32(b)-uint32(n))
  2792  
  2793  		default:
  2794  			c.ctxt.Diag("unexpected op in rldc case\n%v", p)
  2795  		}
  2796  
  2797  	case 16: /* bc bo,bi,bra */
  2798  		a := 0
  2799  
  2800  		r := int(p.Reg)
  2801  
  2802  		if p.From.Type == obj.TYPE_CONST {
  2803  			a = int(c.regoff(&p.From))
  2804  		} else if p.From.Type == obj.TYPE_REG {
  2805  			if r != 0 {
  2806  				c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
  2807  			}
  2808  			// BI values for the CR
  2809  			switch p.From.Reg {
  2810  			case REG_CR0:
  2811  				r = BI_CR0
  2812  			case REG_CR1:
  2813  				r = BI_CR1
  2814  			case REG_CR2:
  2815  				r = BI_CR2
  2816  			case REG_CR3:
  2817  				r = BI_CR3
  2818  			case REG_CR4:
  2819  				r = BI_CR4
  2820  			case REG_CR5:
  2821  				r = BI_CR5
  2822  			case REG_CR6:
  2823  				r = BI_CR6
  2824  			case REG_CR7:
  2825  				r = BI_CR7
  2826  			default:
  2827  				c.ctxt.Diag("unrecognized register: expecting CR\n")
  2828  			}
  2829  		}
  2830  		v := int32(0)
  2831  		if p.To.Target() != nil {
  2832  			v = int32(p.To.Target().Pc - p.Pc)
  2833  		}
  2834  		if v&03 != 0 {
  2835  			c.ctxt.Diag("odd branch target address\n%v", p)
  2836  			v &^= 03
  2837  		}
  2838  
  2839  		if v < -(1<<16) || v >= 1<<15 {
  2840  			c.ctxt.Diag("branch too far\n%v", p)
  2841  		}
  2842  		o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
  2843  
  2844  	case 17:
  2845  		var bo int32
  2846  		bi := int(p.Reg)
  2847  
  2848  		if p.From.Reg == REG_CR {
  2849  			c.ctxt.Diag("unrecognized register: expected CR0-CR7\n")
  2850  		}
  2851  		bi = int(p.From.Reg&0x7) * 4
  2852  
  2853  		bo = BO_BCR
  2854  
  2855  		switch p.As {
  2856  		case ABLT:
  2857  			bi += BI_LT
  2858  		case ABGT:
  2859  			bi += BI_GT
  2860  		case ABEQ:
  2861  			bi += BI_EQ
  2862  		case ABNE:
  2863  			bo = BO_NOTBCR
  2864  			bi += BI_EQ
  2865  		case ABLE:
  2866  			bo = BO_NOTBCR
  2867  			bi += BI_GT
  2868  		case ABGE:
  2869  			bo = BO_NOTBCR
  2870  			bi += BI_LT
  2871  		case ABVS:
  2872  			bi += BI_FU
  2873  		case ABVC:
  2874  			bo = BO_NOTBCR
  2875  			bi += BI_FU
  2876  		default:
  2877  			c.ctxt.Diag("unexpected instruction: expecting BGT, BEQ, BNE, BLE, BGE, BVS, BVC \n%v", p)
  2878  
  2879  		}
  2880  		if oclass(&p.To) == C_LR {
  2881  			o1 = OPVCC(19, 16, 0, 0)
  2882  		} else {
  2883  			c.ctxt.Diag("bad optab entry (17): %d\n%v", p.To.Class, p)
  2884  		}
  2885  
  2886  		o1 = OP_BCR(o1, uint32(bo), uint32(bi))
  2887  
  2888  	case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */
  2889  		var v int32
  2890  		var bh uint32 = 0
  2891  		if p.As == ABC || p.As == ABCL {
  2892  			v = c.regoff(&p.From) & 31
  2893  		} else {
  2894  			v = 20 /* unconditional */
  2895  		}
  2896  		r := int(p.Reg)
  2897  		if r == 0 {
  2898  			r = 0
  2899  		}
  2900  		switch oclass(&p.To) {
  2901  		case C_CTR:
  2902  			o1 = OPVCC(19, 528, 0, 0)
  2903  
  2904  		case C_LR:
  2905  			o1 = OPVCC(19, 16, 0, 0)
  2906  
  2907  		default:
  2908  			c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
  2909  			v = 0
  2910  		}
  2911  
  2912  		// Insert optional branch hint for bclr[l]/bcctr[l]
  2913  		if p.From3Type() != obj.TYPE_NONE {
  2914  			bh = uint32(p.GetFrom3().Offset)
  2915  			if bh == 2 || bh > 3 {
  2916  				log.Fatalf("BH must be 0,1,3 for %v", p)
  2917  			}
  2918  			o1 |= bh << 11
  2919  		}
  2920  
  2921  		if p.As == ABL || p.As == ABCL {
  2922  			o1 |= 1
  2923  		}
  2924  		o1 = OP_BCR(o1, uint32(v), uint32(r))
  2925  
  2926  	case 19: /* mov $lcon,r ==> cau+or */
  2927  		d := c.vregoff(&p.From)
  2928  		if o.ispfx {
  2929  			o1, o2 = pfxadd(p.To.Reg, REG_R0, PFX_R_ABS, d)
  2930  		} else {
  2931  			o1 = loadu32(int(p.To.Reg), d)
  2932  			o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
  2933  		}
  2934  
  2935  	case 20: /* add $ucon,,r | addis $addcon,r,r */
  2936  		v := c.regoff(&p.From)
  2937  
  2938  		r := int(p.Reg)
  2939  		if r == 0 {
  2940  			r = int(p.To.Reg)
  2941  		}
  2942  		o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  2943  
  2944  	case 21: /* or $u32con,rx[,ry] => oris + ori (similar for xor) */
  2945  		var opu, opl uint32
  2946  		r := uint32(p.Reg)
  2947  		if r == 0 {
  2948  			r = uint32(p.To.Reg)
  2949  		}
  2950  		switch p.As {
  2951  		case AOR:
  2952  			opu, opl = OP_ORIS, OP_ORI
  2953  		case AXOR:
  2954  			opu, opl = OP_XORIS, OP_XORI
  2955  		default:
  2956  			c.ctxt.Diag("unhandled opcode.\n%v", p)
  2957  		}
  2958  		o1 = LOP_IRR(opu, uint32(p.To.Reg), r, uint32(p.From.Offset>>16))
  2959  		o2 = LOP_IRR(opl, uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.From.Offset)&0xFFFF)
  2960  
  2961  	case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add, add $s34con,r1 ==> addis+ori+slw+ori+add */
  2962  		if p.To.Reg == REGTMP || p.Reg == REGTMP {
  2963  			c.ctxt.Diag("can't synthesize large constant\n%v", p)
  2964  		}
  2965  		d := c.vregoff(&p.From)
  2966  		r := int(p.Reg)
  2967  		if r == 0 {
  2968  			r = int(p.To.Reg)
  2969  		}
  2970  		if p.From.Sym != nil {
  2971  			c.ctxt.Diag("%v is not supported", p)
  2972  		}
  2973  		if o.ispfx {
  2974  			o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, d)
  2975  		} else if o.size == 8 {
  2976  			o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))          // tmp = uint16(d)
  2977  			o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) // to = tmp + from
  2978  		} else if o.size == 12 {
  2979  			// Note, o1 is ADDIS if d is negative, ORIS otherwise.
  2980  			o1 = loadu32(REGTMP, d)                                          // tmp = d & 0xFFFF0000
  2981  			o2 = loadl16(REGTMP, d)                                          // tmp |= d & 0xFFFF
  2982  			o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) // to = from + tmp
  2983  		} else {
  2984  			// For backwards compatibility with GOPPC64 < 10, generate 34b constants in register.
  2985  			o1 = LOP_IRR(OP_ADDIS, REGZERO, REGTMP, uint32(d>>32)) // tmp = sign_extend((d>>32)&0xFFFF0000)
  2986  			o2 = loadl16(REGTMP, int64(d>>16))                     // tmp |= (d>>16)&0xFFFF
  2987  			o3 = AOP_MD(OP_RLDICR, REGTMP, REGTMP, 16, 63-16)      // tmp <<= 16
  2988  			o4 = loadl16(REGTMP, int64(uint16(d)))                 // tmp |= d&0xFFFF
  2989  			o5 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  2990  		}
  2991  
  2992  	case 23: /* and $lcon/$addcon,r1,r2 ==> oris+ori+and/addi+and */
  2993  		if p.To.Reg == REGTMP || p.Reg == REGTMP {
  2994  			c.ctxt.Diag("can't synthesize large constant\n%v", p)
  2995  		}
  2996  		d := c.vregoff(&p.From)
  2997  		r := int(p.Reg)
  2998  		if r == 0 {
  2999  			r = int(p.To.Reg)
  3000  		}
  3001  
  3002  		// With S16CON operand, generate 2 instructions using ADDI for signed value,
  3003  		// with 32CON operand generate 3 instructions.
  3004  		if o.size == 8 {
  3005  			o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
  3006  			o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  3007  		} else {
  3008  			o1 = loadu32(REGTMP, d)
  3009  			o2 = loadl16(REGTMP, d)
  3010  			o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  3011  		}
  3012  		if p.From.Sym != nil {
  3013  			c.ctxt.Diag("%v is not supported", p)
  3014  		}
  3015  
  3016  	case 24: /* lfd fA,float64(0) -> xxlxor xsA,xsaA,xsaA + fneg for -0 */
  3017  		o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
  3018  		// This is needed for -0.
  3019  		if o.size == 8 {
  3020  			o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
  3021  		}
  3022  
  3023  	case 25:
  3024  		/* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */
  3025  		v := c.regoff(&p.From)
  3026  
  3027  		if v < 0 {
  3028  			v = 0
  3029  		} else if v > 63 {
  3030  			v = 63
  3031  		}
  3032  		r := int(p.Reg)
  3033  		if r == 0 {
  3034  			r = int(p.To.Reg)
  3035  		}
  3036  		var a int
  3037  		op := uint32(0)
  3038  		switch p.As {
  3039  		case ASLD, ASLDCC:
  3040  			a = int(63 - v)
  3041  			op = OP_RLDICR
  3042  
  3043  		case ASRD, ASRDCC:
  3044  			a = int(v)
  3045  			v = 64 - v
  3046  			op = OP_RLDICL
  3047  		case AROTL:
  3048  			a = int(0)
  3049  			op = OP_RLDICL
  3050  		case AEXTSWSLI, AEXTSWSLICC:
  3051  			a = int(v)
  3052  		default:
  3053  			c.ctxt.Diag("unexpected op in sldi case\n%v", p)
  3054  			a = 0
  3055  			o1 = 0
  3056  		}
  3057  
  3058  		if p.As == AEXTSWSLI || p.As == AEXTSWSLICC {
  3059  			o1 = AOP_EXTSWSLI(OP_EXTSWSLI, uint32(r), uint32(p.To.Reg), uint32(v))
  3060  
  3061  		} else {
  3062  			o1 = AOP_MD(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
  3063  		}
  3064  		if p.As == ASLDCC || p.As == ASRDCC || p.As == AEXTSWSLICC {
  3065  			o1 |= 1 // Set the condition code bit
  3066  		}
  3067  
  3068  	case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */
  3069  		v := c.vregoff(&p.From)
  3070  		r := int(p.From.Reg)
  3071  		var rel *obj.Reloc
  3072  
  3073  		switch p.From.Name {
  3074  		case obj.NAME_EXTERN, obj.NAME_STATIC:
  3075  			// Load a 32 bit constant, or relocation depending on if a symbol is attached
  3076  			var rel1 obj.Reloc
  3077  			o1, o2, rel1 = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI, true)
  3078  			rel = &rel1
  3079  		default:
  3080  			// Add a 32 bit offset to a register.
  3081  			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(int32(v))))
  3082  			o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
  3083  		}
  3084  
  3085  		if o.ispfx {
  3086  			if rel == nil {
  3087  				o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, v)
  3088  			} else {
  3089  				o1, o2 = pfxadd(int16(p.To.Reg), REG_R0, PFX_R_PCREL, 0)
  3090  				rel.Type = objabi.R_ADDRPOWER_PCREL34
  3091  			}
  3092  		}
  3093  		if rel != nil {
  3094  			c.cursym.AddRel(c.ctxt, *rel)
  3095  		}
  3096  
  3097  	case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */
  3098  		v := c.regoff(p.GetFrom3())
  3099  
  3100  		r := int(p.From.Reg)
  3101  		o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  3102  
  3103  	case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */
  3104  		if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
  3105  			c.ctxt.Diag("can't synthesize large constant\n%v", p)
  3106  		}
  3107  		v := c.vregoff(p.GetFrom3())
  3108  		o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
  3109  		o2 = loadl16(REGTMP, v)
  3110  		o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
  3111  		if p.From.Sym != nil {
  3112  			c.ctxt.Diag("%v is not supported", p)
  3113  		}
  3114  
  3115  	case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */
  3116  		sh := uint32(c.regoff(&p.From))
  3117  		d := c.vregoff(p.GetFrom3())
  3118  		mb, me, valid := decodeMask64(d)
  3119  		var a uint32
  3120  		switch p.As {
  3121  		case ARLDC, ARLDCCC:
  3122  			a = mb
  3123  			if me != (63-sh) || !valid {
  3124  				c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
  3125  			}
  3126  
  3127  		case ARLDCL, ARLDCLCC:
  3128  			a = mb
  3129  			if mb != 63 || !valid {
  3130  				c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
  3131  			}
  3132  
  3133  		case ARLDCR, ARLDCRCC:
  3134  			a = me
  3135  			if mb != 0 || !valid {
  3136  				c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
  3137  			}
  3138  
  3139  		default:
  3140  			c.ctxt.Diag("unexpected op in rldic case\n%v", p)
  3141  		}
  3142  		o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, a)
  3143  
  3144  	case 30: /* rldimi $sh,s,$mask,a */
  3145  		sh := uint32(c.regoff(&p.From))
  3146  		d := c.vregoff(p.GetFrom3())
  3147  
  3148  		// Original opcodes had mask operands which had to be converted to a shift count as expected by
  3149  		// the ppc64 asm.
  3150  		switch p.As {
  3151  		case ARLDMI, ARLDMICC:
  3152  			mb, me, valid := decodeMask64(d)
  3153  			if me != (63-sh) || !valid {
  3154  				c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), me, sh, p)
  3155  			}
  3156  			o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, mb)
  3157  
  3158  		// Opcodes with shift count operands.
  3159  		case ARLDIMI, ARLDIMICC:
  3160  			o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, uint32(d))
  3161  		}
  3162  
  3163  	case 31: /* dword */
  3164  		d := c.vregoff(&p.From)
  3165  
  3166  		if c.ctxt.Arch.ByteOrder == binary.BigEndian {
  3167  			o1 = uint32(d >> 32)
  3168  			o2 = uint32(d)
  3169  		} else {
  3170  			o1 = uint32(d)
  3171  			o2 = uint32(d >> 32)
  3172  		}
  3173  
  3174  		if p.From.Sym != nil {
  3175  			c.cursym.AddRel(c.ctxt, obj.Reloc{
  3176  				Type: objabi.R_ADDR,
  3177  				Off:  int32(c.pc),
  3178  				Siz:  8,
  3179  				Sym:  p.From.Sym,
  3180  				Add:  p.From.Offset,
  3181  			})
  3182  			o2 = 0
  3183  			o1 = o2
  3184  		}
  3185  
  3186  	case 32: /* fmul frc,fra,frd */
  3187  		r := int(p.Reg)
  3188  
  3189  		if r == 0 {
  3190  			r = int(p.To.Reg)
  3191  		}
  3192  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
  3193  
  3194  	case 33: /* fabs [frb,]frd; fmr. frb,frd */
  3195  		r := int(p.From.Reg)
  3196  
  3197  		if oclass(&p.From) == C_NONE {
  3198  			r = int(p.To.Reg)
  3199  		}
  3200  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
  3201  
  3202  	case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */
  3203  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
  3204  
  3205  	case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */
  3206  		v := c.regoff(&p.To)
  3207  		r := int(p.To.Reg)
  3208  		// Offsets in DS form stores must be a multiple of 4
  3209  		if o.ispfx {
  3210  			o1, o2 = pfxstore(p.As, p.From.Reg, int16(r), PFX_R_ABS)
  3211  			o1 |= uint32((v >> 16) & 0x3FFFF)
  3212  			o2 |= uint32(v & 0xFFFF)
  3213  		} else {
  3214  			inst := c.opstore(p.As)
  3215  			if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3216  				log.Fatalf("invalid offset for DS form load/store %v", p)
  3217  			}
  3218  			o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
  3219  			o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
  3220  		}
  3221  
  3222  	case 36: /* mov b/bz/h/hz lext/lauto/lreg,r ==> lbz+extsb/lbz/lha/lhz etc */
  3223  		v := c.regoff(&p.From)
  3224  		r := int(p.From.Reg)
  3225  
  3226  		if o.ispfx {
  3227  			o1, o2 = pfxload(p.As, p.To.Reg, int16(r), PFX_R_ABS)
  3228  			o1 |= uint32((v >> 16) & 0x3FFFF)
  3229  			o2 |= uint32(v & 0xFFFF)
  3230  		} else {
  3231  			if o.a6 == C_REG {
  3232  				// Reuse the base register when loading a GPR (C_REG) to avoid
  3233  				// using REGTMP (R31) when possible.
  3234  				o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
  3235  				o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
  3236  			} else {
  3237  				o1 = AOP_IRR(OP_ADDIS, uint32(REGTMP), uint32(r), uint32(high16adjusted(v)))
  3238  				o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(REGTMP), uint32(v))
  3239  			}
  3240  		}
  3241  
  3242  		// Sign extend MOVB if needed
  3243  		o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3244  
  3245  	case 40: /* word */
  3246  		o1 = uint32(c.regoff(&p.From))
  3247  
  3248  	case 41: /* stswi */
  3249  		if p.To.Type == obj.TYPE_MEM && p.To.Index == 0 && p.To.Offset != 0 {
  3250  			c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
  3251  		}
  3252  
  3253  		o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
  3254  
  3255  	case 42: /* lswi */
  3256  		if p.From.Type == obj.TYPE_MEM && p.From.Index == 0 && p.From.Offset != 0 {
  3257  			c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
  3258  		}
  3259  		o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
  3260  
  3261  	case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */
  3262  		/* TH field for dcbt/dcbtst: */
  3263  		/* 0 = Block access - program will soon access EA. */
  3264  		/* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */
  3265  		/* 16 = Block access - program will soon make a transient access to EA. */
  3266  		/* 17 = Block access - program will not access EA for a long time. */
  3267  
  3268  		/* L field for dcbf: */
  3269  		/* 0 = invalidates the block containing EA in all processors. */
  3270  		/* 1 = same as 0, but with limited scope (i.e. block in the current processor will not be reused soon). */
  3271  		/* 3 = same as 1, but with even more limited scope (i.e. block in the current processor primary cache will not be reused soon). */
  3272  		if p.To.Type == obj.TYPE_NONE {
  3273  			o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
  3274  		} else {
  3275  			th := c.regoff(&p.To)
  3276  			o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
  3277  		}
  3278  
  3279  	case 44: /* indexed store */
  3280  		o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
  3281  
  3282  	case 45: /* indexed load */
  3283  		switch p.As {
  3284  		/* The assembler accepts a 4-operand l*arx instruction. The fourth operand is an Exclusive Access Hint (EH) */
  3285  		/* The EH field can be used as a lock acquire/release hint as follows: */
  3286  		/* 0 = Atomic Update (fetch-and-operate or similar algorithm) */
  3287  		/* 1 = Exclusive Access (lock acquire and release) */
  3288  		case ALBAR, ALHAR, ALWAR, ALDAR:
  3289  			if p.From3Type() != obj.TYPE_NONE {
  3290  				eh := int(c.regoff(p.GetFrom3()))
  3291  				if eh > 1 {
  3292  					c.ctxt.Diag("illegal EH field\n%v", p)
  3293  				}
  3294  				o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
  3295  			} else {
  3296  				o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3297  			}
  3298  		default:
  3299  			o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3300  		}
  3301  	case 46: /* plain op */
  3302  		o1 = c.oprrr(p.As)
  3303  
  3304  	case 47: /* op Ra, Rd; also op [Ra,] Rd */
  3305  		r := int(p.From.Reg)
  3306  
  3307  		if r == 0 {
  3308  			r = int(p.To.Reg)
  3309  		}
  3310  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
  3311  
  3312  	case 48: /* op Rs, Ra */
  3313  		r := int(p.From.Reg)
  3314  
  3315  		if r == 0 {
  3316  			r = int(p.To.Reg)
  3317  		}
  3318  		o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
  3319  
  3320  	case 49: /* op Rb; op $n, Rb */
  3321  		if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */
  3322  			v := c.regoff(&p.From) & 1
  3323  			o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
  3324  		} else {
  3325  			o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
  3326  		}
  3327  
  3328  	case 50: /* rem[u] r1[,r2],r3 */
  3329  		r := int(p.Reg)
  3330  
  3331  		if r == 0 {
  3332  			r = int(p.To.Reg)
  3333  		}
  3334  		v := c.oprrr(p.As)
  3335  		t := v & (1<<10 | 1) /* OE|Rc */
  3336  		o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
  3337  		o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
  3338  		o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
  3339  		if p.As == AREMU {
  3340  			o4 = o3
  3341  
  3342  			/* Clear top 32 bits */
  3343  			o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
  3344  		}
  3345  
  3346  	case 51: /* remd[u] r1[,r2],r3 */
  3347  		r := int(p.Reg)
  3348  
  3349  		if r == 0 {
  3350  			r = int(p.To.Reg)
  3351  		}
  3352  		v := c.oprrr(p.As)
  3353  		t := v & (1<<10 | 1) /* OE|Rc */
  3354  		o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
  3355  		o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
  3356  		o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
  3357  		/* cases 50,51: removed; can be reused. */
  3358  
  3359  		/* cases 50,51: removed; can be reused. */
  3360  
  3361  	case 52: /* mtfsbNx cr(n) */
  3362  		v := c.regoff(&p.From) & 31
  3363  
  3364  		o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
  3365  
  3366  	case 53: /* mffsX ,fr1 */
  3367  		o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
  3368  
  3369  	case 55: /* op Rb, Rd */
  3370  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
  3371  
  3372  	case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */
  3373  		v := c.regoff(&p.From)
  3374  
  3375  		r := int(p.Reg)
  3376  		if r == 0 {
  3377  			r = int(p.To.Reg)
  3378  		}
  3379  		o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
  3380  		if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
  3381  			o1 |= 1 << 1 /* mb[5] */
  3382  		}
  3383  
  3384  	case 57: /* slw $sh,[s,]a -> rlwinm ... */
  3385  		v := c.regoff(&p.From)
  3386  
  3387  		r := int(p.Reg)
  3388  		if r == 0 {
  3389  			r = int(p.To.Reg)
  3390  		}
  3391  
  3392  		/*
  3393  			 * Let user (gs) shoot himself in the foot.
  3394  			 * qc has already complained.
  3395  			 *
  3396  			if(v < 0 || v > 31)
  3397  				ctxt->diag("illegal shift %ld\n%v", v, p);
  3398  		*/
  3399  		if v < 0 {
  3400  			v = 0
  3401  		} else if v > 32 {
  3402  			v = 32
  3403  		}
  3404  		var mask [2]uint8
  3405  		switch p.As {
  3406  		case AROTLW:
  3407  			mask[0], mask[1] = 0, 31
  3408  		case ASRW, ASRWCC:
  3409  			mask[0], mask[1] = uint8(v), 31
  3410  			v = 32 - v
  3411  		default:
  3412  			mask[0], mask[1] = 0, uint8(31-v)
  3413  		}
  3414  		o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
  3415  		if p.As == ASLWCC || p.As == ASRWCC {
  3416  			o1 |= 1 // set the condition code
  3417  		}
  3418  
  3419  	case 58: /* logical $andcon,[s],a */
  3420  		v := c.regoff(&p.From)
  3421  
  3422  		r := int(p.Reg)
  3423  		if r == 0 {
  3424  			r = int(p.To.Reg)
  3425  		}
  3426  		o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  3427  
  3428  	case 60: /* tw to,a,b */
  3429  		r := int(c.regoff(&p.From) & 31)
  3430  
  3431  		o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
  3432  
  3433  	case 61: /* tw to,a,$simm */
  3434  		r := int(c.regoff(&p.From) & 31)
  3435  
  3436  		v := c.regoff(&p.To)
  3437  		o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
  3438  
  3439  	case 62: /* clrlslwi $sh,s,$mask,a */
  3440  		v := c.regoff(&p.From)
  3441  		n := c.regoff(p.GetFrom3())
  3442  		// This is an extended mnemonic described in the ISA C.8.2
  3443  		// clrlslwi ra,rs,b,n -> rlwinm ra,rs,n,b-n,31-n
  3444  		// It maps onto rlwinm which is directly generated here.
  3445  		if n > v || v >= 32 {
  3446  			c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, n, p)
  3447  		}
  3448  
  3449  		o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(n), uint32(v-n), uint32(31-n))
  3450  
  3451  	case 63: /* rlwimi/rlwnm/rlwinm [$sh,b],s,[$mask or mb,me],a*/
  3452  		var mb, me uint32
  3453  		if len(p.RestArgs) == 1 { // Mask needs decomposed into mb and me.
  3454  			var valid bool
  3455  			// Note, optab rules ensure $mask is a 32b constant.
  3456  			mb, me, valid = decodeMask32(uint32(p.RestArgs[0].Addr.Offset))
  3457  			if !valid {
  3458  				c.ctxt.Diag("cannot generate mask #%x\n%v", uint64(p.RestArgs[0].Addr.Offset), p)
  3459  			}
  3460  		} else { // Otherwise, mask is already passed as mb and me in RestArgs.
  3461  			mb, me = uint32(p.RestArgs[0].Addr.Offset), uint32(p.RestArgs[1].Addr.Offset)
  3462  		}
  3463  		if p.From.Type == obj.TYPE_CONST {
  3464  			o1 = OP_RLW(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Offset), mb, me)
  3465  		} else {
  3466  			o1 = OP_RLW(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), mb, me)
  3467  		}
  3468  
  3469  	case 64: /* mtfsf fr[, $m] {,fpcsr} */
  3470  		var v int32
  3471  		if p.From3Type() != obj.TYPE_NONE {
  3472  			v = c.regoff(p.GetFrom3()) & 255
  3473  		} else {
  3474  			v = 255
  3475  		}
  3476  		o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
  3477  
  3478  	case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */
  3479  		if p.To.Reg == 0 {
  3480  			c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
  3481  		}
  3482  		o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
  3483  
  3484  	case 66: /* mov spr,r1; mov r1,spr */
  3485  		var r int
  3486  		var v int32
  3487  		if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
  3488  			r = int(p.From.Reg)
  3489  			v = int32(p.To.Reg)
  3490  			o1 = OPVCC(31, 467, 0, 0) /* mtspr */
  3491  		} else {
  3492  			r = int(p.To.Reg)
  3493  			v = int32(p.From.Reg)
  3494  			o1 = OPVCC(31, 339, 0, 0) /* mfspr */
  3495  		}
  3496  
  3497  		o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
  3498  
  3499  	case 67: /* mcrf crfD,crfS */
  3500  		if p.From.Reg == REG_CR || p.To.Reg == REG_CR {
  3501  			c.ctxt.Diag("CR argument must be a conditional register field (CR0-CR7)\n%v", p)
  3502  		}
  3503  		o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
  3504  
  3505  	case 68: /* mfcr rD; mfocrf CRM,rD */
  3506  		o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /*  form, whole register */
  3507  		if p.From.Reg != REG_CR {
  3508  			v := uint32(1) << uint(7-(p.From.Reg&7)) /* CR(n) */
  3509  			o1 |= 1<<20 | v<<12                      /* new form, mfocrf */
  3510  		}
  3511  
  3512  	case 69: /* mtcrf CRM,rS, mtocrf CRx,rS */
  3513  		var v uint32
  3514  		if p.To.Reg == REG_CR {
  3515  			v = 0xff
  3516  		} else if p.To.Offset != 0 { // MOVFL gpr, constant
  3517  			v = uint32(p.To.Offset)
  3518  		} else { // p.To.Reg == REG_CRx
  3519  			v = 1 << uint(7-(p.To.Reg&7))
  3520  		}
  3521  		// Use mtocrf form if only one CR field moved.
  3522  		if bits.OnesCount32(v) == 1 {
  3523  			v |= 1 << 8
  3524  		}
  3525  
  3526  		o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12
  3527  
  3528  	case 70: /* cmp* r,r,cr or cmp*i r,i,cr or fcmp f,f,cr or cmpeqb r,r */
  3529  		r := uint32(p.Reg&7) << 2
  3530  		if p.To.Type == obj.TYPE_CONST {
  3531  			o1 = AOP_IRR(c.opirr(p.As), r, uint32(p.From.Reg), uint32(uint16(p.To.Offset)))
  3532  		} else {
  3533  			o1 = AOP_RRR(c.oprrr(p.As), r, uint32(p.From.Reg), uint32(p.To.Reg))
  3534  		}
  3535  
  3536  	case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */
  3537  		o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
  3538  
  3539  	case 73: /* mcrfs crfD,crfS */
  3540  		if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
  3541  			c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
  3542  		}
  3543  		o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
  3544  
  3545  	case 77: /* syscall $scon, syscall Rx */
  3546  		if p.From.Type == obj.TYPE_CONST {
  3547  			if p.From.Offset > BIG || p.From.Offset < -BIG {
  3548  				c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
  3549  			}
  3550  			o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
  3551  		} else if p.From.Type == obj.TYPE_REG {
  3552  			o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
  3553  		} else {
  3554  			c.ctxt.Diag("illegal syscall: %v", p)
  3555  			o1 = 0x7fe00008 // trap always
  3556  		}
  3557  
  3558  		o2 = c.oprrr(p.As)
  3559  		o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0
  3560  
  3561  	case 78: /* undef */
  3562  		o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed
  3563  		   always to be an illegal instruction."  */
  3564  
  3565  	/* relocation operations */
  3566  	case 74:
  3567  		v := c.vregoff(&p.To)
  3568  		// Offsets in DS form stores must be a multiple of 4
  3569  		inst := c.opstore(p.As)
  3570  
  3571  		// Can't reuse base for store instructions.
  3572  		var rel obj.Reloc
  3573  		o1, o2, rel = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst, false)
  3574  
  3575  		// Rewrite as a prefixed store if supported.
  3576  		if o.ispfx {
  3577  			o1, o2 = pfxstore(p.As, p.From.Reg, REG_R0, PFX_R_PCREL)
  3578  			rel.Type = objabi.R_ADDRPOWER_PCREL34
  3579  		} else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3580  			log.Fatalf("invalid offset for DS form load/store %v", p)
  3581  		}
  3582  		c.cursym.AddRel(c.ctxt, rel)
  3583  
  3584  	case 75: // 32 bit offset symbol loads (got/toc/addr)
  3585  		v := p.From.Offset
  3586  
  3587  		// Offsets in DS form loads must be a multiple of 4
  3588  		inst := c.opload(p.As)
  3589  		var rel obj.Reloc
  3590  		switch p.From.Name {
  3591  		case obj.NAME_GOTREF, obj.NAME_TOCREF:
  3592  			if v != 0 {
  3593  				c.ctxt.Diag("invalid offset for GOT/TOC access %v", p)
  3594  			}
  3595  			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
  3596  			o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3597  			rel.Off = int32(c.pc)
  3598  			rel.Siz = 8
  3599  			rel.Sym = p.From.Sym
  3600  			switch p.From.Name {
  3601  			case obj.NAME_GOTREF:
  3602  				rel.Type = objabi.R_ADDRPOWER_GOT
  3603  			case obj.NAME_TOCREF:
  3604  				rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
  3605  			}
  3606  		default:
  3607  			reuseBaseReg := o.a6 == C_REG
  3608  			// Reuse To.Reg as base register if it is a GPR.
  3609  			o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
  3610  		}
  3611  
  3612  		// Convert to prefixed forms if supported.
  3613  		if o.ispfx {
  3614  			switch rel.Type {
  3615  			case objabi.R_ADDRPOWER, objabi.R_ADDRPOWER_DS,
  3616  				objabi.R_ADDRPOWER_TOCREL, objabi.R_ADDRPOWER_TOCREL_DS:
  3617  				o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
  3618  				rel.Type = objabi.R_ADDRPOWER_PCREL34
  3619  			case objabi.R_POWER_TLS_IE:
  3620  				o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
  3621  				rel.Type = objabi.R_POWER_TLS_IE_PCREL34
  3622  			case objabi.R_ADDRPOWER_GOT:
  3623  				o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
  3624  				rel.Type = objabi.R_ADDRPOWER_GOT_PCREL34
  3625  			default:
  3626  				// We've failed to convert a TOC-relative relocation to a PC-relative one.
  3627  				log.Fatalf("Unable convert TOC-relative relocation %v to PC-relative", rel.Type)
  3628  			}
  3629  		} else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3630  			log.Fatalf("invalid offset for DS form load/store %v", p)
  3631  		}
  3632  		c.cursym.AddRel(c.ctxt, rel)
  3633  
  3634  		o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3635  
  3636  	case 79:
  3637  		if p.From.Offset != 0 {
  3638  			c.ctxt.Diag("invalid offset against tls var %v", p)
  3639  		}
  3640  		var typ objabi.RelocType
  3641  		if !o.ispfx {
  3642  			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R13, 0)
  3643  			o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3644  			typ = objabi.R_POWER_TLS_LE
  3645  		} else {
  3646  			o1, o2 = pfxadd(p.To.Reg, REG_R13, PFX_R_ABS, 0)
  3647  			typ = objabi.R_POWER_TLS_LE_TPREL34
  3648  		}
  3649  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  3650  			Type: typ,
  3651  			Off:  int32(c.pc),
  3652  			Siz:  8,
  3653  			Sym:  p.From.Sym,
  3654  		})
  3655  
  3656  	case 80:
  3657  		if p.From.Offset != 0 {
  3658  			c.ctxt.Diag("invalid offset against tls var %v", p)
  3659  		}
  3660  		typ := objabi.R_POWER_TLS_IE
  3661  		if !o.ispfx {
  3662  			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
  3663  			o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3664  		} else {
  3665  			o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
  3666  			typ = objabi.R_POWER_TLS_IE_PCREL34
  3667  		}
  3668  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  3669  			Type: typ,
  3670  			Off:  int32(c.pc),
  3671  			Siz:  8,
  3672  			Sym:  p.From.Sym,
  3673  		})
  3674  		o3 = AOP_RRR(OP_ADD, uint32(p.To.Reg), uint32(p.To.Reg), REG_R13)
  3675  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  3676  			Type: objabi.R_POWER_TLS,
  3677  			Off:  int32(c.pc) + 8,
  3678  			Siz:  4,
  3679  			Sym:  p.From.Sym,
  3680  		})
  3681  
  3682  	case 82: /* vector instructions, VX-form and VC-form */
  3683  		if p.From.Type == obj.TYPE_REG {
  3684  			/* reg reg none OR reg reg reg */
  3685  			/* 3-register operand order: VRA, VRB, VRT */
  3686  			/* 2-register operand order: VRA, VRT */
  3687  			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3688  		} else if p.From3Type() == obj.TYPE_CONST {
  3689  			/* imm imm reg reg */
  3690  			/* operand order: SIX, VRA, ST, VRT */
  3691  			six := int(c.regoff(&p.From))
  3692  			st := int(c.regoff(p.GetFrom3()))
  3693  			o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
  3694  		} else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
  3695  			/* imm reg reg */
  3696  			/* operand order: UIM, VRB, VRT */
  3697  			uim := int(c.regoff(&p.From))
  3698  			o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
  3699  		} else {
  3700  			/* imm reg */
  3701  			/* operand order: SIM, VRT */
  3702  			sim := int(c.regoff(&p.From))
  3703  			o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
  3704  		}
  3705  
  3706  	case 83: /* vector instructions, VA-form */
  3707  		if p.From.Type == obj.TYPE_REG {
  3708  			/* reg reg reg reg */
  3709  			/* 4-register operand order: VRA, VRB, VRC, VRT */
  3710  			o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
  3711  		} else if p.From.Type == obj.TYPE_CONST {
  3712  			/* imm reg reg reg */
  3713  			/* operand order: SHB, VRA, VRB, VRT */
  3714  			shb := int(c.regoff(&p.From))
  3715  			o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
  3716  		}
  3717  
  3718  	case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc
  3719  		bc := c.vregoff(&p.From)
  3720  		if o.a1 == C_CRBIT {
  3721  			// CR bit is encoded as a register, not a constant.
  3722  			bc = int64(p.From.Reg)
  3723  		}
  3724  
  3725  		// rt = To.Reg, ra = p.Reg, rb = p.From3.Reg
  3726  		o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
  3727  
  3728  	case 85: /* vector instructions, VX-form */
  3729  		/* reg none reg */
  3730  		/* 2-register operand order: VRB, VRT */
  3731  		o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
  3732  
  3733  	case 86: /* VSX indexed store, XX1-form */
  3734  		/* reg reg reg */
  3735  		/* 3-register operand order: XT, (RB)(RA*1) */
  3736  		o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
  3737  
  3738  	case 87: /* VSX indexed load, XX1-form */
  3739  		/* reg reg reg */
  3740  		/* 3-register operand order: (RB)(RA*1), XT */
  3741  		o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3742  
  3743  	case 88: /* VSX mfvsr* instructions, XX1-form XS,RA */
  3744  		o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
  3745  
  3746  	case 89: /* VSX instructions, XX2-form */
  3747  		/* reg none reg OR reg imm reg */
  3748  		/* 2-register operand order: XB, XT or XB, UIM, XT*/
  3749  		uim := int(c.regoff(p.GetFrom3()))
  3750  		o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
  3751  
  3752  	case 90: /* VSX instructions, XX3-form */
  3753  		if p.From3Type() == obj.TYPE_NONE {
  3754  			/* reg reg reg */
  3755  			/* 3-register operand order: XA, XB, XT */
  3756  			o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3757  		} else if p.From3Type() == obj.TYPE_CONST {
  3758  			/* reg reg reg imm */
  3759  			/* operand order: XA, XB, DM, XT */
  3760  			dm := int(c.regoff(p.GetFrom3()))
  3761  			o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
  3762  		}
  3763  
  3764  	case 91: /* VSX instructions, XX4-form */
  3765  		/* reg reg reg reg */
  3766  		/* 3-register operand order: XA, XB, XC, XT */
  3767  		o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
  3768  
  3769  	case 92: /* X-form instructions, 3-operands */
  3770  		if p.To.Type == obj.TYPE_CONST {
  3771  			/* imm reg reg */
  3772  			xf := int32(p.From.Reg)
  3773  			if REG_F0 <= xf && xf <= REG_F31 {
  3774  				/* operand order: FRA, FRB, BF */
  3775  				bf := int(c.regoff(&p.To)) << 2
  3776  				o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
  3777  			} else {
  3778  				/* operand order: RA, RB, L */
  3779  				l := int(c.regoff(&p.To))
  3780  				o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
  3781  			}
  3782  		} else if p.From3Type() == obj.TYPE_CONST {
  3783  			/* reg reg imm */
  3784  			/* operand order: RB, L, RA */
  3785  			l := int(c.regoff(p.GetFrom3()))
  3786  			o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
  3787  		} else if p.To.Type == obj.TYPE_REG {
  3788  			cr := int32(p.To.Reg)
  3789  			if REG_CR0 <= cr && cr <= REG_CR7 {
  3790  				/* cr reg reg */
  3791  				/* operand order: RA, RB, BF */
  3792  				bf := (int(p.To.Reg) & 7) << 2
  3793  				o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
  3794  			} else if p.From.Type == obj.TYPE_CONST {
  3795  				/* reg imm */
  3796  				/* operand order: L, RT */
  3797  				l := int(c.regoff(&p.From))
  3798  				o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
  3799  			} else {
  3800  				switch p.As {
  3801  				case ACOPY, APASTECC:
  3802  					o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
  3803  				default:
  3804  					/* reg reg reg */
  3805  					/* operand order: RS, RB, RA */
  3806  					o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
  3807  				}
  3808  			}
  3809  		}
  3810  
  3811  	case 93: /* X-form instructions, 2-operands */
  3812  		if p.To.Type == obj.TYPE_CONST {
  3813  			/* imm reg */
  3814  			/* operand order: FRB, BF */
  3815  			bf := int(c.regoff(&p.To)) << 2
  3816  			o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
  3817  		} else if p.Reg == 0 {
  3818  			/* popcnt* r,r, X-form */
  3819  			/* operand order: RS, RA */
  3820  			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
  3821  		}
  3822  
  3823  	case 94: /* Z23-form instructions, 4-operands */
  3824  		/* reg reg reg imm */
  3825  		/* operand order: RA, RB, CY, RT */
  3826  		cy := int(c.regoff(p.GetFrom3()))
  3827  		o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
  3828  
  3829  	case 96: /* VSX load, DQ-form */
  3830  		/* reg imm reg */
  3831  		/* operand order: (RA)(DQ), XT */
  3832  		dq := int16(c.regoff(&p.From))
  3833  		if (dq & 15) != 0 {
  3834  			c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
  3835  		}
  3836  		o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq))
  3837  
  3838  	case 97: /* VSX store, DQ-form */
  3839  		/* reg imm reg */
  3840  		/* operand order: XT, (RA)(DQ) */
  3841  		dq := int16(c.regoff(&p.To))
  3842  		if (dq & 15) != 0 {
  3843  			c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
  3844  		}
  3845  		o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq))
  3846  	case 98: /* VSX indexed load or load with length (also left-justified), x-form */
  3847  		/* vsreg, reg, reg */
  3848  		o1 = AOP_XX1(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3849  	case 99: /* VSX store with length (also left-justified) x-form */
  3850  		/* reg, reg, vsreg */
  3851  		o1 = AOP_XX1(c.opstore(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
  3852  	case 100: /* VSX X-form XXSPLTIB */
  3853  		if p.From.Type == obj.TYPE_CONST {
  3854  			/* imm reg */
  3855  			uim := int(c.regoff(&p.From))
  3856  			/* imm reg */
  3857  			/* Use AOP_XX1 form with 0 for one of the registers. */
  3858  			o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(uim))
  3859  		} else {
  3860  			c.ctxt.Diag("invalid ops for %v", p.As)
  3861  		}
  3862  	case 101:
  3863  		o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg))
  3864  
  3865  	case 104: /* VSX mtvsr* instructions, XX1-form RA,RB,XT */
  3866  		o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3867  
  3868  	case 106: /* MOVD spr, soreg */
  3869  		v := int32(p.From.Reg)
  3870  		o1 = OPVCC(31, 339, 0, 0) /* mfspr */
  3871  		o1 = AOP_RRR(o1, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
  3872  		so := c.regoff(&p.To)
  3873  		o2 = AOP_IRR(c.opstore(AMOVD), uint32(REGTMP), uint32(p.To.Reg), uint32(so))
  3874  		if so&0x3 != 0 {
  3875  			log.Fatalf("invalid offset for DS form load/store %v", p)
  3876  		}
  3877  		if p.To.Reg == REGTMP {
  3878  			log.Fatalf("SPR move to memory will clobber R31 %v", p)
  3879  		}
  3880  
  3881  	case 107: /* MOVD soreg, spr */
  3882  		v := int32(p.From.Reg)
  3883  		so := c.regoff(&p.From)
  3884  		o1 = AOP_IRR(c.opload(AMOVD), uint32(REGTMP), uint32(v), uint32(so))
  3885  		o2 = OPVCC(31, 467, 0, 0) /* mtspr */
  3886  		v = int32(p.To.Reg)
  3887  		o2 = AOP_RRR(o2, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
  3888  		if so&0x3 != 0 {
  3889  			log.Fatalf("invalid offset for DS form load/store %v", p)
  3890  		}
  3891  
  3892  	case 108: /* mov r, xoreg ==> stwx rx,ry */
  3893  		r := int(p.To.Reg)
  3894  		o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
  3895  
  3896  	case 109: /* mov xoreg, r ==> lbzx/lhzx/lwzx rx,ry, lbzx rx,ry + extsb r,r */
  3897  		r := int(p.From.Reg)
  3898  
  3899  		o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
  3900  		// Sign extend MOVB operations. This is ignored for other cases (o.size == 4).
  3901  		o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3902  
  3903  	case 110: /* SETB creg, rt */
  3904  		bfa := uint32(p.From.Reg) << 2
  3905  		rt := uint32(p.To.Reg)
  3906  		o1 = LOP_RRR(OP_SETB, bfa, rt, 0)
  3907  	}
  3908  
  3909  	out[0] = o1
  3910  	out[1] = o2
  3911  	out[2] = o3
  3912  	out[3] = o4
  3913  	out[4] = o5
  3914  }
  3915  
  3916  func (c *ctxt9) vregoff(a *obj.Addr) int64 {
  3917  	c.instoffset = 0
  3918  	if a != nil {
  3919  		c.aclass(a)
  3920  	}
  3921  	return c.instoffset
  3922  }
  3923  
  3924  func (c *ctxt9) regoff(a *obj.Addr) int32 {
  3925  	return int32(c.vregoff(a))
  3926  }
  3927  
  3928  func (c *ctxt9) oprrr(a obj.As) uint32 {
  3929  	switch a {
  3930  	case AADD:
  3931  		return OPVCC(31, 266, 0, 0)
  3932  	case AADDCC:
  3933  		return OPVCC(31, 266, 0, 1)
  3934  	case AADDV:
  3935  		return OPVCC(31, 266, 1, 0)
  3936  	case AADDVCC:
  3937  		return OPVCC(31, 266, 1, 1)
  3938  	case AADDC:
  3939  		return OPVCC(31, 10, 0, 0)
  3940  	case AADDCCC:
  3941  		return OPVCC(31, 10, 0, 1)
  3942  	case AADDCV:
  3943  		return OPVCC(31, 10, 1, 0)
  3944  	case AADDCVCC:
  3945  		return OPVCC(31, 10, 1, 1)
  3946  	case AADDE:
  3947  		return OPVCC(31, 138, 0, 0)
  3948  	case AADDECC:
  3949  		return OPVCC(31, 138, 0, 1)
  3950  	case AADDEV:
  3951  		return OPVCC(31, 138, 1, 0)
  3952  	case AADDEVCC:
  3953  		return OPVCC(31, 138, 1, 1)
  3954  	case AADDME:
  3955  		return OPVCC(31, 234, 0, 0)
  3956  	case AADDMECC:
  3957  		return OPVCC(31, 234, 0, 1)
  3958  	case AADDMEV:
  3959  		return OPVCC(31, 234, 1, 0)
  3960  	case AADDMEVCC:
  3961  		return OPVCC(31, 234, 1, 1)
  3962  	case AADDZE:
  3963  		return OPVCC(31, 202, 0, 0)
  3964  	case AADDZECC:
  3965  		return OPVCC(31, 202, 0, 1)
  3966  	case AADDZEV:
  3967  		return OPVCC(31, 202, 1, 0)
  3968  	case AADDZEVCC:
  3969  		return OPVCC(31, 202, 1, 1)
  3970  	case AADDEX:
  3971  		return OPVCC(31, 170, 0, 0) /* addex - v3.0b */
  3972  
  3973  	case AAND:
  3974  		return OPVCC(31, 28, 0, 0)
  3975  	case AANDCC:
  3976  		return OPVCC(31, 28, 0, 1)
  3977  	case AANDN:
  3978  		return OPVCC(31, 60, 0, 0)
  3979  	case AANDNCC:
  3980  		return OPVCC(31, 60, 0, 1)
  3981  
  3982  	case ACMP:
  3983  		return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */
  3984  	case ACMPU:
  3985  		return OPVCC(31, 32, 0, 0) | 1<<21
  3986  	case ACMPW:
  3987  		return OPVCC(31, 0, 0, 0) /* L=0 */
  3988  	case ACMPWU:
  3989  		return OPVCC(31, 32, 0, 0)
  3990  	case ACMPB:
  3991  		return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */
  3992  	case ACMPEQB:
  3993  		return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */
  3994  
  3995  	case ACNTLZW:
  3996  		return OPVCC(31, 26, 0, 0)
  3997  	case ACNTLZWCC:
  3998  		return OPVCC(31, 26, 0, 1)
  3999  	case ACNTLZD:
  4000  		return OPVCC(31, 58, 0, 0)
  4001  	case ACNTLZDCC:
  4002  		return OPVCC(31, 58, 0, 1)
  4003  
  4004  	case ACRAND:
  4005  		return OPVCC(19, 257, 0, 0)
  4006  	case ACRANDN:
  4007  		return OPVCC(19, 129, 0, 0)
  4008  	case ACREQV:
  4009  		return OPVCC(19, 289, 0, 0)
  4010  	case ACRNAND:
  4011  		return OPVCC(19, 225, 0, 0)
  4012  	case ACRNOR:
  4013  		return OPVCC(19, 33, 0, 0)
  4014  	case ACROR:
  4015  		return OPVCC(19, 449, 0, 0)
  4016  	case ACRORN:
  4017  		return OPVCC(19, 417, 0, 0)
  4018  	case ACRXOR:
  4019  		return OPVCC(19, 193, 0, 0)
  4020  
  4021  	case ADADD:
  4022  		return OPVCC(59, 2, 0, 0)
  4023  	case ADDIV:
  4024  		return OPVCC(59, 546, 0, 0)
  4025  	case ADMUL:
  4026  		return OPVCC(59, 34, 0, 0)
  4027  	case ADSUB:
  4028  		return OPVCC(59, 514, 0, 0)
  4029  	case ADADDQ:
  4030  		return OPVCC(63, 2, 0, 0)
  4031  	case ADDIVQ:
  4032  		return OPVCC(63, 546, 0, 0)
  4033  	case ADMULQ:
  4034  		return OPVCC(63, 34, 0, 0)
  4035  	case ADSUBQ:
  4036  		return OPVCC(63, 514, 0, 0)
  4037  	case ADCMPU:
  4038  		return OPVCC(59, 642, 0, 0)
  4039  	case ADCMPUQ:
  4040  		return OPVCC(63, 642, 0, 0)
  4041  	case ADCMPO:
  4042  		return OPVCC(59, 130, 0, 0)
  4043  	case ADCMPOQ:
  4044  		return OPVCC(63, 130, 0, 0)
  4045  
  4046  	case ADCBF:
  4047  		return OPVCC(31, 86, 0, 0)
  4048  	case ADCBI:
  4049  		return OPVCC(31, 470, 0, 0)
  4050  	case ADCBST:
  4051  		return OPVCC(31, 54, 0, 0)
  4052  	case ADCBT:
  4053  		return OPVCC(31, 278, 0, 0)
  4054  	case ADCBTST:
  4055  		return OPVCC(31, 246, 0, 0)
  4056  	case ADCBZ:
  4057  		return OPVCC(31, 1014, 0, 0)
  4058  
  4059  	case AMODUD:
  4060  		return OPVCC(31, 265, 0, 0) /* modud - v3.0 */
  4061  	case AMODUW:
  4062  		return OPVCC(31, 267, 0, 0) /* moduw - v3.0 */
  4063  	case AMODSD:
  4064  		return OPVCC(31, 777, 0, 0) /* modsd - v3.0 */
  4065  	case AMODSW:
  4066  		return OPVCC(31, 779, 0, 0) /* modsw - v3.0 */
  4067  
  4068  	case ADIVW, AREM:
  4069  		return OPVCC(31, 491, 0, 0)
  4070  
  4071  	case ADIVWCC:
  4072  		return OPVCC(31, 491, 0, 1)
  4073  
  4074  	case ADIVWV:
  4075  		return OPVCC(31, 491, 1, 0)
  4076  
  4077  	case ADIVWVCC:
  4078  		return OPVCC(31, 491, 1, 1)
  4079  
  4080  	case ADIVWU, AREMU:
  4081  		return OPVCC(31, 459, 0, 0)
  4082  
  4083  	case ADIVWUCC:
  4084  		return OPVCC(31, 459, 0, 1)
  4085  
  4086  	case ADIVWUV:
  4087  		return OPVCC(31, 459, 1, 0)
  4088  
  4089  	case ADIVWUVCC:
  4090  		return OPVCC(31, 459, 1, 1)
  4091  
  4092  	case ADIVD, AREMD:
  4093  		return OPVCC(31, 489, 0, 0)
  4094  
  4095  	case ADIVDCC:
  4096  		return OPVCC(31, 489, 0, 1)
  4097  
  4098  	case ADIVDE:
  4099  		return OPVCC(31, 425, 0, 0)
  4100  
  4101  	case ADIVDECC:
  4102  		return OPVCC(31, 425, 0, 1)
  4103  
  4104  	case ADIVDEU:
  4105  		return OPVCC(31, 393, 0, 0)
  4106  
  4107  	case ADIVDEUCC:
  4108  		return OPVCC(31, 393, 0, 1)
  4109  
  4110  	case ADIVDV:
  4111  		return OPVCC(31, 489, 1, 0)
  4112  
  4113  	case ADIVDVCC:
  4114  		return OPVCC(31, 489, 1, 1)
  4115  
  4116  	case ADIVDU, AREMDU:
  4117  		return OPVCC(31, 457, 0, 0)
  4118  
  4119  	case ADIVDUCC:
  4120  		return OPVCC(31, 457, 0, 1)
  4121  
  4122  	case ADIVDUV:
  4123  		return OPVCC(31, 457, 1, 0)
  4124  
  4125  	case ADIVDUVCC:
  4126  		return OPVCC(31, 457, 1, 1)
  4127  
  4128  	case AEIEIO:
  4129  		return OPVCC(31, 854, 0, 0)
  4130  
  4131  	case AEQV:
  4132  		return OPVCC(31, 284, 0, 0)
  4133  	case AEQVCC:
  4134  		return OPVCC(31, 284, 0, 1)
  4135  
  4136  	case AEXTSB:
  4137  		return OPVCC(31, 954, 0, 0)
  4138  	case AEXTSBCC:
  4139  		return OPVCC(31, 954, 0, 1)
  4140  	case AEXTSH:
  4141  		return OPVCC(31, 922, 0, 0)
  4142  	case AEXTSHCC:
  4143  		return OPVCC(31, 922, 0, 1)
  4144  	case AEXTSW:
  4145  		return OPVCC(31, 986, 0, 0)
  4146  	case AEXTSWCC:
  4147  		return OPVCC(31, 986, 0, 1)
  4148  
  4149  	case AFABS:
  4150  		return OPVCC(63, 264, 0, 0)
  4151  	case AFABSCC:
  4152  		return OPVCC(63, 264, 0, 1)
  4153  	case AFADD:
  4154  		return OPVCC(63, 21, 0, 0)
  4155  	case AFADDCC:
  4156  		return OPVCC(63, 21, 0, 1)
  4157  	case AFADDS:
  4158  		return OPVCC(59, 21, 0, 0)
  4159  	case AFADDSCC:
  4160  		return OPVCC(59, 21, 0, 1)
  4161  	case AFCMPO:
  4162  		return OPVCC(63, 32, 0, 0)
  4163  	case AFCMPU:
  4164  		return OPVCC(63, 0, 0, 0)
  4165  	case AFCFID:
  4166  		return OPVCC(63, 846, 0, 0)
  4167  	case AFCFIDCC:
  4168  		return OPVCC(63, 846, 0, 1)
  4169  	case AFCFIDU:
  4170  		return OPVCC(63, 974, 0, 0)
  4171  	case AFCFIDUCC:
  4172  		return OPVCC(63, 974, 0, 1)
  4173  	case AFCFIDS:
  4174  		return OPVCC(59, 846, 0, 0)
  4175  	case AFCFIDSCC:
  4176  		return OPVCC(59, 846, 0, 1)
  4177  	case AFCTIW:
  4178  		return OPVCC(63, 14, 0, 0)
  4179  	case AFCTIWCC:
  4180  		return OPVCC(63, 14, 0, 1)
  4181  	case AFCTIWZ:
  4182  		return OPVCC(63, 15, 0, 0)
  4183  	case AFCTIWZCC:
  4184  		return OPVCC(63, 15, 0, 1)
  4185  	case AFCTID:
  4186  		return OPVCC(63, 814, 0, 0)
  4187  	case AFCTIDCC:
  4188  		return OPVCC(63, 814, 0, 1)
  4189  	case AFCTIDZ:
  4190  		return OPVCC(63, 815, 0, 0)
  4191  	case AFCTIDZCC:
  4192  		return OPVCC(63, 815, 0, 1)
  4193  	case AFDIV:
  4194  		return OPVCC(63, 18, 0, 0)
  4195  	case AFDIVCC:
  4196  		return OPVCC(63, 18, 0, 1)
  4197  	case AFDIVS:
  4198  		return OPVCC(59, 18, 0, 0)
  4199  	case AFDIVSCC:
  4200  		return OPVCC(59, 18, 0, 1)
  4201  	case AFMADD:
  4202  		return OPVCC(63, 29, 0, 0)
  4203  	case AFMADDCC:
  4204  		return OPVCC(63, 29, 0, 1)
  4205  	case AFMADDS:
  4206  		return OPVCC(59, 29, 0, 0)
  4207  	case AFMADDSCC:
  4208  		return OPVCC(59, 29, 0, 1)
  4209  
  4210  	case AFMOVS, AFMOVD:
  4211  		return OPVCC(63, 72, 0, 0) /* load */
  4212  	case AFMOVDCC:
  4213  		return OPVCC(63, 72, 0, 1)
  4214  	case AFMSUB:
  4215  		return OPVCC(63, 28, 0, 0)
  4216  	case AFMSUBCC:
  4217  		return OPVCC(63, 28, 0, 1)
  4218  	case AFMSUBS:
  4219  		return OPVCC(59, 28, 0, 0)
  4220  	case AFMSUBSCC:
  4221  		return OPVCC(59, 28, 0, 1)
  4222  	case AFMUL:
  4223  		return OPVCC(63, 25, 0, 0)
  4224  	case AFMULCC:
  4225  		return OPVCC(63, 25, 0, 1)
  4226  	case AFMULS:
  4227  		return OPVCC(59, 25, 0, 0)
  4228  	case AFMULSCC:
  4229  		return OPVCC(59, 25, 0, 1)
  4230  	case AFNABS:
  4231  		return OPVCC(63, 136, 0, 0)
  4232  	case AFNABSCC:
  4233  		return OPVCC(63, 136, 0, 1)
  4234  	case AFNEG:
  4235  		return OPVCC(63, 40, 0, 0)
  4236  	case AFNEGCC:
  4237  		return OPVCC(63, 40, 0, 1)
  4238  	case AFNMADD:
  4239  		return OPVCC(63, 31, 0, 0)
  4240  	case AFNMADDCC:
  4241  		return OPVCC(63, 31, 0, 1)
  4242  	case AFNMADDS:
  4243  		return OPVCC(59, 31, 0, 0)
  4244  	case AFNMADDSCC:
  4245  		return OPVCC(59, 31, 0, 1)
  4246  	case AFNMSUB:
  4247  		return OPVCC(63, 30, 0, 0)
  4248  	case AFNMSUBCC:
  4249  		return OPVCC(63, 30, 0, 1)
  4250  	case AFNMSUBS:
  4251  		return OPVCC(59, 30, 0, 0)
  4252  	case AFNMSUBSCC:
  4253  		return OPVCC(59, 30, 0, 1)
  4254  	case AFCPSGN:
  4255  		return OPVCC(63, 8, 0, 0)
  4256  	case AFCPSGNCC:
  4257  		return OPVCC(63, 8, 0, 1)
  4258  	case AFRES:
  4259  		return OPVCC(59, 24, 0, 0)
  4260  	case AFRESCC:
  4261  		return OPVCC(59, 24, 0, 1)
  4262  	case AFRIM:
  4263  		return OPVCC(63, 488, 0, 0)
  4264  	case AFRIMCC:
  4265  		return OPVCC(63, 488, 0, 1)
  4266  	case AFRIP:
  4267  		return OPVCC(63, 456, 0, 0)
  4268  	case AFRIPCC:
  4269  		return OPVCC(63, 456, 0, 1)
  4270  	case AFRIZ:
  4271  		return OPVCC(63, 424, 0, 0)
  4272  	case AFRIZCC:
  4273  		return OPVCC(63, 424, 0, 1)
  4274  	case AFRIN:
  4275  		return OPVCC(63, 392, 0, 0)
  4276  	case AFRINCC:
  4277  		return OPVCC(63, 392, 0, 1)
  4278  	case AFRSP:
  4279  		return OPVCC(63, 12, 0, 0)
  4280  	case AFRSPCC:
  4281  		return OPVCC(63, 12, 0, 1)
  4282  	case AFRSQRTE:
  4283  		return OPVCC(63, 26, 0, 0)
  4284  	case AFRSQRTECC:
  4285  		return OPVCC(63, 26, 0, 1)
  4286  	case AFSEL:
  4287  		return OPVCC(63, 23, 0, 0)
  4288  	case AFSELCC:
  4289  		return OPVCC(63, 23, 0, 1)
  4290  	case AFSQRT:
  4291  		return OPVCC(63, 22, 0, 0)
  4292  	case AFSQRTCC:
  4293  		return OPVCC(63, 22, 0, 1)
  4294  	case AFSQRTS:
  4295  		return OPVCC(59, 22, 0, 0)
  4296  	case AFSQRTSCC:
  4297  		return OPVCC(59, 22, 0, 1)
  4298  	case AFSUB:
  4299  		return OPVCC(63, 20, 0, 0)
  4300  	case AFSUBCC:
  4301  		return OPVCC(63, 20, 0, 1)
  4302  	case AFSUBS:
  4303  		return OPVCC(59, 20, 0, 0)
  4304  	case AFSUBSCC:
  4305  		return OPVCC(59, 20, 0, 1)
  4306  
  4307  	case AICBI:
  4308  		return OPVCC(31, 982, 0, 0)
  4309  	case AISYNC:
  4310  		return OPVCC(19, 150, 0, 0)
  4311  
  4312  	case AMTFSB0:
  4313  		return OPVCC(63, 70, 0, 0)
  4314  	case AMTFSB0CC:
  4315  		return OPVCC(63, 70, 0, 1)
  4316  	case AMTFSB1:
  4317  		return OPVCC(63, 38, 0, 0)
  4318  	case AMTFSB1CC:
  4319  		return OPVCC(63, 38, 0, 1)
  4320  
  4321  	case AMULHW:
  4322  		return OPVCC(31, 75, 0, 0)
  4323  	case AMULHWCC:
  4324  		return OPVCC(31, 75, 0, 1)
  4325  	case AMULHWU:
  4326  		return OPVCC(31, 11, 0, 0)
  4327  	case AMULHWUCC:
  4328  		return OPVCC(31, 11, 0, 1)
  4329  	case AMULLW:
  4330  		return OPVCC(31, 235, 0, 0)
  4331  	case AMULLWCC:
  4332  		return OPVCC(31, 235, 0, 1)
  4333  	case AMULLWV:
  4334  		return OPVCC(31, 235, 1, 0)
  4335  	case AMULLWVCC:
  4336  		return OPVCC(31, 235, 1, 1)
  4337  
  4338  	case AMULHD:
  4339  		return OPVCC(31, 73, 0, 0)
  4340  	case AMULHDCC:
  4341  		return OPVCC(31, 73, 0, 1)
  4342  	case AMULHDU:
  4343  		return OPVCC(31, 9, 0, 0)
  4344  	case AMULHDUCC:
  4345  		return OPVCC(31, 9, 0, 1)
  4346  	case AMULLD:
  4347  		return OPVCC(31, 233, 0, 0)
  4348  	case AMULLDCC:
  4349  		return OPVCC(31, 233, 0, 1)
  4350  	case AMULLDV:
  4351  		return OPVCC(31, 233, 1, 0)
  4352  	case AMULLDVCC:
  4353  		return OPVCC(31, 233, 1, 1)
  4354  
  4355  	case ANAND:
  4356  		return OPVCC(31, 476, 0, 0)
  4357  	case ANANDCC:
  4358  		return OPVCC(31, 476, 0, 1)
  4359  	case ANEG:
  4360  		return OPVCC(31, 104, 0, 0)
  4361  	case ANEGCC:
  4362  		return OPVCC(31, 104, 0, 1)
  4363  	case ANEGV:
  4364  		return OPVCC(31, 104, 1, 0)
  4365  	case ANEGVCC:
  4366  		return OPVCC(31, 104, 1, 1)
  4367  	case ANOR:
  4368  		return OPVCC(31, 124, 0, 0)
  4369  	case ANORCC:
  4370  		return OPVCC(31, 124, 0, 1)
  4371  	case AOR:
  4372  		return OPVCC(31, 444, 0, 0)
  4373  	case AORCC:
  4374  		return OPVCC(31, 444, 0, 1)
  4375  	case AORN:
  4376  		return OPVCC(31, 412, 0, 0)
  4377  	case AORNCC:
  4378  		return OPVCC(31, 412, 0, 1)
  4379  
  4380  	case APOPCNTD:
  4381  		return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */
  4382  	case APOPCNTW:
  4383  		return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */
  4384  	case APOPCNTB:
  4385  		return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */
  4386  	case ACNTTZW:
  4387  		return OPVCC(31, 538, 0, 0) /* cnttzw - v3.00 */
  4388  	case ACNTTZWCC:
  4389  		return OPVCC(31, 538, 0, 1) /* cnttzw. - v3.00 */
  4390  	case ACNTTZD:
  4391  		return OPVCC(31, 570, 0, 0) /* cnttzd - v3.00 */
  4392  	case ACNTTZDCC:
  4393  		return OPVCC(31, 570, 0, 1) /* cnttzd. - v3.00 */
  4394  
  4395  	case ARFI:
  4396  		return OPVCC(19, 50, 0, 0)
  4397  	case ARFCI:
  4398  		return OPVCC(19, 51, 0, 0)
  4399  	case ARFID:
  4400  		return OPVCC(19, 18, 0, 0)
  4401  	case AHRFID:
  4402  		return OPVCC(19, 274, 0, 0)
  4403  
  4404  	case ARLWNM:
  4405  		return OPVCC(23, 0, 0, 0)
  4406  	case ARLWNMCC:
  4407  		return OPVCC(23, 0, 0, 1)
  4408  
  4409  	case ARLDCL:
  4410  		return OPVCC(30, 8, 0, 0)
  4411  	case ARLDCLCC:
  4412  		return OPVCC(30, 0, 0, 1)
  4413  
  4414  	case ARLDCR:
  4415  		return OPVCC(30, 9, 0, 0)
  4416  	case ARLDCRCC:
  4417  		return OPVCC(30, 9, 0, 1)
  4418  
  4419  	case ARLDICL:
  4420  		return OPVCC(30, 0, 0, 0)
  4421  	case ARLDICLCC:
  4422  		return OPVCC(30, 0, 0, 1)
  4423  	case ARLDICR:
  4424  		return OPMD(30, 1, 0) // rldicr
  4425  	case ARLDICRCC:
  4426  		return OPMD(30, 1, 1) // rldicr.
  4427  
  4428  	case ARLDIC:
  4429  		return OPMD(30, 2, 0) // rldic
  4430  	case ARLDICCC:
  4431  		return OPMD(30, 2, 1) // rldic.
  4432  
  4433  	case ASYSCALL:
  4434  		return OPVCC(17, 1, 0, 0)
  4435  
  4436  	case ASLW:
  4437  		return OPVCC(31, 24, 0, 0)
  4438  	case ASLWCC:
  4439  		return OPVCC(31, 24, 0, 1)
  4440  	case ASLD:
  4441  		return OPVCC(31, 27, 0, 0)
  4442  	case ASLDCC:
  4443  		return OPVCC(31, 27, 0, 1)
  4444  
  4445  	case ASRAW:
  4446  		return OPVCC(31, 792, 0, 0)
  4447  	case ASRAWCC:
  4448  		return OPVCC(31, 792, 0, 1)
  4449  	case ASRAD:
  4450  		return OPVCC(31, 794, 0, 0)
  4451  	case ASRADCC:
  4452  		return OPVCC(31, 794, 0, 1)
  4453  
  4454  	case AEXTSWSLI:
  4455  		return OPVCC(31, 445, 0, 0)
  4456  	case AEXTSWSLICC:
  4457  		return OPVCC(31, 445, 0, 1)
  4458  
  4459  	case ASRW:
  4460  		return OPVCC(31, 536, 0, 0)
  4461  	case ASRWCC:
  4462  		return OPVCC(31, 536, 0, 1)
  4463  	case ASRD:
  4464  		return OPVCC(31, 539, 0, 0)
  4465  	case ASRDCC:
  4466  		return OPVCC(31, 539, 0, 1)
  4467  
  4468  	case ASUB:
  4469  		return OPVCC(31, 40, 0, 0)
  4470  	case ASUBCC:
  4471  		return OPVCC(31, 40, 0, 1)
  4472  	case ASUBV:
  4473  		return OPVCC(31, 40, 1, 0)
  4474  	case ASUBVCC:
  4475  		return OPVCC(31, 40, 1, 1)
  4476  	case ASUBC:
  4477  		return OPVCC(31, 8, 0, 0)
  4478  	case ASUBCCC:
  4479  		return OPVCC(31, 8, 0, 1)
  4480  	case ASUBCV:
  4481  		return OPVCC(31, 8, 1, 0)
  4482  	case ASUBCVCC:
  4483  		return OPVCC(31, 8, 1, 1)
  4484  	case ASUBE:
  4485  		return OPVCC(31, 136, 0, 0)
  4486  	case ASUBECC:
  4487  		return OPVCC(31, 136, 0, 1)
  4488  	case ASUBEV:
  4489  		return OPVCC(31, 136, 1, 0)
  4490  	case ASUBEVCC:
  4491  		return OPVCC(31, 136, 1, 1)
  4492  	case ASUBME:
  4493  		return OPVCC(31, 232, 0, 0)
  4494  	case ASUBMECC:
  4495  		return OPVCC(31, 232, 0, 1)
  4496  	case ASUBMEV:
  4497  		return OPVCC(31, 232, 1, 0)
  4498  	case ASUBMEVCC:
  4499  		return OPVCC(31, 232, 1, 1)
  4500  	case ASUBZE:
  4501  		return OPVCC(31, 200, 0, 0)
  4502  	case ASUBZECC:
  4503  		return OPVCC(31, 200, 0, 1)
  4504  	case ASUBZEV:
  4505  		return OPVCC(31, 200, 1, 0)
  4506  	case ASUBZEVCC:
  4507  		return OPVCC(31, 200, 1, 1)
  4508  
  4509  	case ASYNC:
  4510  		return OPVCC(31, 598, 0, 0)
  4511  	case ALWSYNC:
  4512  		return OPVCC(31, 598, 0, 0) | 1<<21
  4513  
  4514  	case APTESYNC:
  4515  		return OPVCC(31, 598, 0, 0) | 2<<21
  4516  
  4517  	case ATLBIE:
  4518  		return OPVCC(31, 306, 0, 0)
  4519  	case ATLBIEL:
  4520  		return OPVCC(31, 274, 0, 0)
  4521  	case ATLBSYNC:
  4522  		return OPVCC(31, 566, 0, 0)
  4523  	case ASLBIA:
  4524  		return OPVCC(31, 498, 0, 0)
  4525  	case ASLBIE:
  4526  		return OPVCC(31, 434, 0, 0)
  4527  	case ASLBMFEE:
  4528  		return OPVCC(31, 915, 0, 0)
  4529  	case ASLBMFEV:
  4530  		return OPVCC(31, 851, 0, 0)
  4531  	case ASLBMTE:
  4532  		return OPVCC(31, 402, 0, 0)
  4533  
  4534  	case ATW:
  4535  		return OPVCC(31, 4, 0, 0)
  4536  	case ATD:
  4537  		return OPVCC(31, 68, 0, 0)
  4538  
  4539  	/* Vector (VMX/Altivec) instructions */
  4540  	/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  4541  	/* are enabled starting at POWER6 (ISA 2.05). */
  4542  	case AVAND:
  4543  		return OPVX(4, 1028, 0, 0) /* vand - v2.03 */
  4544  	case AVANDC:
  4545  		return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */
  4546  	case AVNAND:
  4547  		return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */
  4548  
  4549  	case AVOR:
  4550  		return OPVX(4, 1156, 0, 0) /* vor - v2.03 */
  4551  	case AVORC:
  4552  		return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */
  4553  	case AVNOR:
  4554  		return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */
  4555  	case AVXOR:
  4556  		return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */
  4557  	case AVEQV:
  4558  		return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */
  4559  
  4560  	case AVADDUBM:
  4561  		return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */
  4562  	case AVADDUHM:
  4563  		return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */
  4564  	case AVADDUWM:
  4565  		return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */
  4566  	case AVADDUDM:
  4567  		return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */
  4568  	case AVADDUQM:
  4569  		return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */
  4570  
  4571  	case AVADDCUQ:
  4572  		return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */
  4573  	case AVADDCUW:
  4574  		return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */
  4575  
  4576  	case AVADDUBS:
  4577  		return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */
  4578  	case AVADDUHS:
  4579  		return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */
  4580  	case AVADDUWS:
  4581  		return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */
  4582  
  4583  	case AVADDSBS:
  4584  		return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */
  4585  	case AVADDSHS:
  4586  		return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */
  4587  	case AVADDSWS:
  4588  		return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */
  4589  
  4590  	case AVADDEUQM:
  4591  		return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */
  4592  	case AVADDECUQ:
  4593  		return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */
  4594  
  4595  	case AVMULESB:
  4596  		return OPVX(4, 776, 0, 0) /* vmulesb - v2.03 */
  4597  	case AVMULOSB:
  4598  		return OPVX(4, 264, 0, 0) /* vmulosb - v2.03 */
  4599  	case AVMULEUB:
  4600  		return OPVX(4, 520, 0, 0) /* vmuleub - v2.03 */
  4601  	case AVMULOUB:
  4602  		return OPVX(4, 8, 0, 0) /* vmuloub - v2.03 */
  4603  	case AVMULESH:
  4604  		return OPVX(4, 840, 0, 0) /* vmulesh - v2.03 */
  4605  	case AVMULOSH:
  4606  		return OPVX(4, 328, 0, 0) /* vmulosh - v2.03 */
  4607  	case AVMULEUH:
  4608  		return OPVX(4, 584, 0, 0) /* vmuleuh - v2.03 */
  4609  	case AVMULOUH:
  4610  		return OPVX(4, 72, 0, 0) /* vmulouh - v2.03 */
  4611  	case AVMULESW:
  4612  		return OPVX(4, 904, 0, 0) /* vmulesw - v2.07 */
  4613  	case AVMULOSW:
  4614  		return OPVX(4, 392, 0, 0) /* vmulosw - v2.07 */
  4615  	case AVMULEUW:
  4616  		return OPVX(4, 648, 0, 0) /* vmuleuw - v2.07 */
  4617  	case AVMULOUW:
  4618  		return OPVX(4, 136, 0, 0) /* vmulouw - v2.07 */
  4619  	case AVMULUWM:
  4620  		return OPVX(4, 137, 0, 0) /* vmuluwm - v2.07 */
  4621  
  4622  	case AVPMSUMB:
  4623  		return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */
  4624  	case AVPMSUMH:
  4625  		return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */
  4626  	case AVPMSUMW:
  4627  		return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */
  4628  	case AVPMSUMD:
  4629  		return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */
  4630  
  4631  	case AVMSUMUDM:
  4632  		return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */
  4633  
  4634  	case AVSUBUBM:
  4635  		return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */
  4636  	case AVSUBUHM:
  4637  		return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */
  4638  	case AVSUBUWM:
  4639  		return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */
  4640  	case AVSUBUDM:
  4641  		return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */
  4642  	case AVSUBUQM:
  4643  		return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */
  4644  
  4645  	case AVSUBCUQ:
  4646  		return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */
  4647  	case AVSUBCUW:
  4648  		return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */
  4649  
  4650  	case AVSUBUBS:
  4651  		return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */
  4652  	case AVSUBUHS:
  4653  		return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */
  4654  	case AVSUBUWS:
  4655  		return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */
  4656  
  4657  	case AVSUBSBS:
  4658  		return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */
  4659  	case AVSUBSHS:
  4660  		return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */
  4661  	case AVSUBSWS:
  4662  		return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */
  4663  
  4664  	case AVSUBEUQM:
  4665  		return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */
  4666  	case AVSUBECUQ:
  4667  		return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */
  4668  
  4669  	case AVRLB:
  4670  		return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */
  4671  	case AVRLH:
  4672  		return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */
  4673  	case AVRLW:
  4674  		return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */
  4675  	case AVRLD:
  4676  		return OPVX(4, 196, 0, 0) /* vrld - v2.07 */
  4677  
  4678  	case AVMRGOW:
  4679  		return OPVX(4, 1676, 0, 0) /* vmrgow - v2.07 */
  4680  	case AVMRGEW:
  4681  		return OPVX(4, 1932, 0, 0) /* vmrgew - v2.07 */
  4682  
  4683  	case AVSLB:
  4684  		return OPVX(4, 260, 0, 0) /* vslh - v2.03 */
  4685  	case AVSLH:
  4686  		return OPVX(4, 324, 0, 0) /* vslh - v2.03 */
  4687  	case AVSLW:
  4688  		return OPVX(4, 388, 0, 0) /* vslw - v2.03 */
  4689  	case AVSL:
  4690  		return OPVX(4, 452, 0, 0) /* vsl - v2.03 */
  4691  	case AVSLO:
  4692  		return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */
  4693  	case AVSRB:
  4694  		return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */
  4695  	case AVSRH:
  4696  		return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */
  4697  	case AVSRW:
  4698  		return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */
  4699  	case AVSR:
  4700  		return OPVX(4, 708, 0, 0) /* vsr - v2.03 */
  4701  	case AVSRO:
  4702  		return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */
  4703  	case AVSLD:
  4704  		return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */
  4705  	case AVSRD:
  4706  		return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */
  4707  
  4708  	case AVSRAB:
  4709  		return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */
  4710  	case AVSRAH:
  4711  		return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */
  4712  	case AVSRAW:
  4713  		return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */
  4714  	case AVSRAD:
  4715  		return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */
  4716  
  4717  	case AVBPERMQ:
  4718  		return OPVC(4, 1356, 0, 0) /* vbpermq - v2.07 */
  4719  	case AVBPERMD:
  4720  		return OPVC(4, 1484, 0, 0) /* vbpermd - v3.00 */
  4721  
  4722  	case AVCLZB:
  4723  		return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */
  4724  	case AVCLZH:
  4725  		return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */
  4726  	case AVCLZW:
  4727  		return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */
  4728  	case AVCLZD:
  4729  		return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */
  4730  
  4731  	case AVCLZLSBB:
  4732  		return OPVX(4, 1538, 0, 0) /* vclzlsbb - v3.0 */
  4733  	case AVCTZLSBB:
  4734  		return OPVX(4, 1538, 0, 0) | 1<<16 /* vctzlsbb - v3.0 */
  4735  
  4736  	case AVPOPCNTB:
  4737  		return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */
  4738  	case AVPOPCNTH:
  4739  		return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */
  4740  	case AVPOPCNTW:
  4741  		return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */
  4742  	case AVPOPCNTD:
  4743  		return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */
  4744  
  4745  	case AVCMPEQUB:
  4746  		return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */
  4747  	case AVCMPEQUBCC:
  4748  		return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */
  4749  	case AVCMPEQUH:
  4750  		return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */
  4751  	case AVCMPEQUHCC:
  4752  		return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */
  4753  	case AVCMPEQUW:
  4754  		return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */
  4755  	case AVCMPEQUWCC:
  4756  		return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */
  4757  	case AVCMPEQUD:
  4758  		return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */
  4759  	case AVCMPEQUDCC:
  4760  		return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */
  4761  
  4762  	case AVCMPGTUB:
  4763  		return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */
  4764  	case AVCMPGTUBCC:
  4765  		return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */
  4766  	case AVCMPGTUH:
  4767  		return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */
  4768  	case AVCMPGTUHCC:
  4769  		return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */
  4770  	case AVCMPGTUW:
  4771  		return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */
  4772  	case AVCMPGTUWCC:
  4773  		return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */
  4774  	case AVCMPGTUD:
  4775  		return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */
  4776  	case AVCMPGTUDCC:
  4777  		return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */
  4778  	case AVCMPGTSB:
  4779  		return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */
  4780  	case AVCMPGTSBCC:
  4781  		return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */
  4782  	case AVCMPGTSH:
  4783  		return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */
  4784  	case AVCMPGTSHCC:
  4785  		return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */
  4786  	case AVCMPGTSW:
  4787  		return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */
  4788  	case AVCMPGTSWCC:
  4789  		return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */
  4790  	case AVCMPGTSD:
  4791  		return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */
  4792  	case AVCMPGTSDCC:
  4793  		return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */
  4794  
  4795  	case AVCMPNEZB:
  4796  		return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */
  4797  	case AVCMPNEZBCC:
  4798  		return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */
  4799  	case AVCMPNEB:
  4800  		return OPVC(4, 7, 0, 0) /* vcmpneb - v3.00 */
  4801  	case AVCMPNEBCC:
  4802  		return OPVC(4, 7, 0, 1) /* vcmpneb. - v3.00 */
  4803  	case AVCMPNEH:
  4804  		return OPVC(4, 71, 0, 0) /* vcmpneh - v3.00 */
  4805  	case AVCMPNEHCC:
  4806  		return OPVC(4, 71, 0, 1) /* vcmpneh. - v3.00 */
  4807  	case AVCMPNEW:
  4808  		return OPVC(4, 135, 0, 0) /* vcmpnew - v3.00 */
  4809  	case AVCMPNEWCC:
  4810  		return OPVC(4, 135, 0, 1) /* vcmpnew. - v3.00 */
  4811  
  4812  	case AVPERM:
  4813  		return OPVX(4, 43, 0, 0) /* vperm - v2.03 */
  4814  	case AVPERMXOR:
  4815  		return OPVX(4, 45, 0, 0) /* vpermxor - v2.03 */
  4816  	case AVPERMR:
  4817  		return OPVX(4, 59, 0, 0) /* vpermr - v3.0 */
  4818  
  4819  	case AVSEL:
  4820  		return OPVX(4, 42, 0, 0) /* vsel - v2.03 */
  4821  
  4822  	case AVCIPHER:
  4823  		return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */
  4824  	case AVCIPHERLAST:
  4825  		return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */
  4826  	case AVNCIPHER:
  4827  		return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */
  4828  	case AVNCIPHERLAST:
  4829  		return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */
  4830  	case AVSBOX:
  4831  		return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */
  4832  	/* End of vector instructions */
  4833  
  4834  	/* Vector scalar (VSX) instructions */
  4835  	/* ISA 2.06 enables these for POWER7. */
  4836  	case AMFVSRD, AMFVRD, AMFFPRD:
  4837  		return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */
  4838  	case AMFVSRWZ:
  4839  		return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */
  4840  	case AMFVSRLD:
  4841  		return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */
  4842  
  4843  	case AMTVSRD, AMTFPRD, AMTVRD:
  4844  		return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */
  4845  	case AMTVSRWA:
  4846  		return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */
  4847  	case AMTVSRWZ:
  4848  		return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */
  4849  	case AMTVSRDD:
  4850  		return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */
  4851  	case AMTVSRWS:
  4852  		return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */
  4853  
  4854  	case AXXLAND:
  4855  		return OPVXX3(60, 130, 0) /* xxland - v2.06 */
  4856  	case AXXLANDC:
  4857  		return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */
  4858  	case AXXLEQV:
  4859  		return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */
  4860  	case AXXLNAND:
  4861  		return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */
  4862  
  4863  	case AXXLORC:
  4864  		return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */
  4865  	case AXXLNOR:
  4866  		return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */
  4867  	case AXXLOR, AXXLORQ:
  4868  		return OPVXX3(60, 146, 0) /* xxlor - v2.06 */
  4869  	case AXXLXOR:
  4870  		return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */
  4871  	case AXSMINJDP:
  4872  		return OPVXX3(60, 152, 0) /* xsminjdp - v3.0 */
  4873  	case AXSMAXJDP:
  4874  		return OPVXX3(60, 144, 0) /* xsmaxjdp - v3.0 */
  4875  
  4876  	case AXXSEL:
  4877  		return OPVXX4(60, 3, 0) /* xxsel - v2.06 */
  4878  
  4879  	case AXXMRGHW:
  4880  		return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */
  4881  	case AXXMRGLW:
  4882  		return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */
  4883  
  4884  	case AXXSPLTW:
  4885  		return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */
  4886  
  4887  	case AXXSPLTIB:
  4888  		return OPVCC(60, 360, 0, 0) /* xxspltib - v3.0 */
  4889  
  4890  	case AXXPERM:
  4891  		return OPVXX3(60, 26, 0) /* xxperm - v2.06 */
  4892  	case AXXPERMDI:
  4893  		return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */
  4894  
  4895  	case AXXSLDWI:
  4896  		return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */
  4897  
  4898  	case AXXBRQ:
  4899  		return OPVXX2VA(60, 475, 31) /* xxbrq - v3.0 */
  4900  	case AXXBRD:
  4901  		return OPVXX2VA(60, 475, 23) /* xxbrd - v3.0 */
  4902  	case AXXBRW:
  4903  		return OPVXX2VA(60, 475, 15) /* xxbrw - v3.0 */
  4904  	case AXXBRH:
  4905  		return OPVXX2VA(60, 475, 7) /* xxbrh - v3.0 */
  4906  
  4907  	case AXSCVDPSP:
  4908  		return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */
  4909  	case AXSCVSPDP:
  4910  		return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */
  4911  	case AXSCVDPSPN:
  4912  		return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */
  4913  	case AXSCVSPDPN:
  4914  		return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */
  4915  
  4916  	case AXVCVDPSP:
  4917  		return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */
  4918  	case AXVCVSPDP:
  4919  		return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */
  4920  
  4921  	case AXSCVDPSXDS:
  4922  		return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */
  4923  	case AXSCVDPSXWS:
  4924  		return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */
  4925  	case AXSCVDPUXDS:
  4926  		return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */
  4927  	case AXSCVDPUXWS:
  4928  		return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */
  4929  
  4930  	case AXSCVSXDDP:
  4931  		return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */
  4932  	case AXSCVUXDDP:
  4933  		return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */
  4934  	case AXSCVSXDSP:
  4935  		return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */
  4936  	case AXSCVUXDSP:
  4937  		return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */
  4938  
  4939  	case AXVCVDPSXDS:
  4940  		return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */
  4941  	case AXVCVDPSXWS:
  4942  		return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */
  4943  	case AXVCVDPUXDS:
  4944  		return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */
  4945  	case AXVCVDPUXWS:
  4946  		return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */
  4947  	case AXVCVSPSXDS:
  4948  		return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */
  4949  	case AXVCVSPSXWS:
  4950  		return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */
  4951  	case AXVCVSPUXDS:
  4952  		return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */
  4953  	case AXVCVSPUXWS:
  4954  		return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */
  4955  
  4956  	case AXVCVSXDDP:
  4957  		return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */
  4958  	case AXVCVSXWDP:
  4959  		return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */
  4960  	case AXVCVUXDDP:
  4961  		return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */
  4962  	case AXVCVUXWDP:
  4963  		return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */
  4964  	case AXVCVSXDSP:
  4965  		return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */
  4966  	case AXVCVSXWSP:
  4967  		return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */
  4968  	case AXVCVUXDSP:
  4969  		return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */
  4970  	case AXVCVUXWSP:
  4971  		return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */
  4972  	/* End of VSX instructions */
  4973  
  4974  	case AMADDHD:
  4975  		return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */
  4976  	case AMADDHDU:
  4977  		return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */
  4978  	case AMADDLD:
  4979  		return OPVX(4, 51, 0, 0) /* maddld - v3.00 */
  4980  
  4981  	case AXOR:
  4982  		return OPVCC(31, 316, 0, 0)
  4983  	case AXORCC:
  4984  		return OPVCC(31, 316, 0, 1)
  4985  	}
  4986  
  4987  	c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
  4988  	return 0
  4989  }
  4990  
  4991  func (c *ctxt9) opirrr(a obj.As) uint32 {
  4992  	switch a {
  4993  	/* Vector (VMX/Altivec) instructions */
  4994  	/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  4995  	/* are enabled starting at POWER6 (ISA 2.05). */
  4996  	case AVSLDOI:
  4997  		return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */
  4998  	}
  4999  
  5000  	c.ctxt.Diag("bad i/r/r/r opcode %v", a)
  5001  	return 0
  5002  }
  5003  
  5004  func (c *ctxt9) opiirr(a obj.As) uint32 {
  5005  	switch a {
  5006  	/* Vector (VMX/Altivec) instructions */
  5007  	/* ISA 2.07 enables these for POWER8 and beyond. */
  5008  	case AVSHASIGMAW:
  5009  		return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */
  5010  	case AVSHASIGMAD:
  5011  		return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */
  5012  	}
  5013  
  5014  	c.ctxt.Diag("bad i/i/r/r opcode %v", a)
  5015  	return 0
  5016  }
  5017  
  5018  func (c *ctxt9) opirr(a obj.As) uint32 {
  5019  	switch a {
  5020  	case AADD:
  5021  		return OPVCC(14, 0, 0, 0)
  5022  	case AADDC:
  5023  		return OPVCC(12, 0, 0, 0)
  5024  	case AADDCCC:
  5025  		return OPVCC(13, 0, 0, 0)
  5026  	case AADDIS:
  5027  		return OPVCC(15, 0, 0, 0) /* ADDIS */
  5028  
  5029  	case AANDCC:
  5030  		return OPVCC(28, 0, 0, 0)
  5031  	case AANDISCC:
  5032  		return OPVCC(29, 0, 0, 0) /* ANDIS. */
  5033  
  5034  	case ABR:
  5035  		return OPVCC(18, 0, 0, 0)
  5036  	case ABL:
  5037  		return OPVCC(18, 0, 0, 0) | 1
  5038  	case obj.ADUFFZERO:
  5039  		return OPVCC(18, 0, 0, 0) | 1
  5040  	case obj.ADUFFCOPY:
  5041  		return OPVCC(18, 0, 0, 0) | 1
  5042  	case ABC:
  5043  		return OPVCC(16, 0, 0, 0)
  5044  	case ABCL:
  5045  		return OPVCC(16, 0, 0, 0) | 1
  5046  
  5047  	case ABEQ:
  5048  		return AOP_RRR(16<<26, BO_BCR, BI_EQ, 0)
  5049  	case ABGE:
  5050  		return AOP_RRR(16<<26, BO_NOTBCR, BI_LT, 0)
  5051  	case ABGT:
  5052  		return AOP_RRR(16<<26, BO_BCR, BI_GT, 0)
  5053  	case ABLE:
  5054  		return AOP_RRR(16<<26, BO_NOTBCR, BI_GT, 0)
  5055  	case ABLT:
  5056  		return AOP_RRR(16<<26, BO_BCR, BI_LT, 0)
  5057  	case ABNE:
  5058  		return AOP_RRR(16<<26, BO_NOTBCR, BI_EQ, 0)
  5059  	case ABVC:
  5060  		return AOP_RRR(16<<26, BO_NOTBCR, BI_FU, 0)
  5061  	case ABVS:
  5062  		return AOP_RRR(16<<26, BO_BCR, BI_FU, 0)
  5063  	case ABDZ:
  5064  		return AOP_RRR(16<<26, BO_NOTBCTR, 0, 0)
  5065  	case ABDNZ:
  5066  		return AOP_RRR(16<<26, BO_BCTR, 0, 0)
  5067  
  5068  	case ACMP:
  5069  		return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */
  5070  	case ACMPU:
  5071  		return OPVCC(10, 0, 0, 0) | 1<<21
  5072  	case ACMPW:
  5073  		return OPVCC(11, 0, 0, 0) /* L=0 */
  5074  	case ACMPWU:
  5075  		return OPVCC(10, 0, 0, 0)
  5076  	case ACMPEQB:
  5077  		return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */
  5078  
  5079  	case ALSW:
  5080  		return OPVCC(31, 597, 0, 0)
  5081  
  5082  	case ACOPY:
  5083  		return OPVCC(31, 774, 0, 0) /* copy - v3.00 */
  5084  	case APASTECC:
  5085  		return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */
  5086  	case ADARN:
  5087  		return OPVCC(31, 755, 0, 0) /* darn - v3.00 */
  5088  
  5089  	case AMULLW, AMULLD:
  5090  		return OPVCC(7, 0, 0, 0) /* mulli works with MULLW or MULLD */
  5091  
  5092  	case AOR:
  5093  		return OPVCC(24, 0, 0, 0)
  5094  	case AORIS:
  5095  		return OPVCC(25, 0, 0, 0) /* ORIS */
  5096  
  5097  	case ARLWMI:
  5098  		return OPVCC(20, 0, 0, 0) /* rlwimi */
  5099  	case ARLWMICC:
  5100  		return OPVCC(20, 0, 0, 1)
  5101  	case ARLDMI:
  5102  		return OPMD(30, 3, 0) /* rldimi */
  5103  	case ARLDMICC:
  5104  		return OPMD(30, 3, 1) /* rldimi. */
  5105  	case ARLDIMI:
  5106  		return OPMD(30, 3, 0) /* rldimi */
  5107  	case ARLDIMICC:
  5108  		return OPMD(30, 3, 1) /* rldimi. */
  5109  	case ARLWNM:
  5110  		return OPVCC(21, 0, 0, 0) /* rlwinm */
  5111  	case ARLWNMCC:
  5112  		return OPVCC(21, 0, 0, 1)
  5113  
  5114  	case ARLDCL:
  5115  		return OPMD(30, 0, 0) /* rldicl */
  5116  	case ARLDCLCC:
  5117  		return OPMD(30, 0, 1) /* rldicl. */
  5118  	case ARLDCR:
  5119  		return OPMD(30, 1, 0) /* rldicr */
  5120  	case ARLDCRCC:
  5121  		return OPMD(30, 1, 1) /* rldicr. */
  5122  	case ARLDC:
  5123  		return OPMD(30, 2, 0) /* rldic */
  5124  	case ARLDCCC:
  5125  		return OPMD(30, 2, 1) /* rldic. */
  5126  
  5127  	case ASRAW:
  5128  		return OPVCC(31, 824, 0, 0)
  5129  	case ASRAWCC:
  5130  		return OPVCC(31, 824, 0, 1)
  5131  	case ASRAD:
  5132  		return OPVCC(31, (413 << 1), 0, 0)
  5133  	case ASRADCC:
  5134  		return OPVCC(31, (413 << 1), 0, 1)
  5135  	case AEXTSWSLI:
  5136  		return OPVCC(31, 445, 0, 0)
  5137  	case AEXTSWSLICC:
  5138  		return OPVCC(31, 445, 0, 1)
  5139  
  5140  	case ASTSW:
  5141  		return OPVCC(31, 725, 0, 0)
  5142  
  5143  	case ASUBC:
  5144  		return OPVCC(8, 0, 0, 0)
  5145  
  5146  	case ATW:
  5147  		return OPVCC(3, 0, 0, 0)
  5148  	case ATD:
  5149  		return OPVCC(2, 0, 0, 0)
  5150  
  5151  	/* Vector (VMX/Altivec) instructions */
  5152  	/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  5153  	/* are enabled starting at POWER6 (ISA 2.05). */
  5154  	case AVSPLTB:
  5155  		return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */
  5156  	case AVSPLTH:
  5157  		return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */
  5158  	case AVSPLTW:
  5159  		return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */
  5160  
  5161  	case AVSPLTISB:
  5162  		return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */
  5163  	case AVSPLTISH:
  5164  		return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */
  5165  	case AVSPLTISW:
  5166  		return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */
  5167  	/* End of vector instructions */
  5168  
  5169  	case AFTDIV:
  5170  		return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */
  5171  	case AFTSQRT:
  5172  		return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */
  5173  
  5174  	case AXOR:
  5175  		return OPVCC(26, 0, 0, 0) /* XORIL */
  5176  	case AXORIS:
  5177  		return OPVCC(27, 0, 0, 0) /* XORIS */
  5178  	}
  5179  
  5180  	c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
  5181  	return 0
  5182  }
  5183  
  5184  /*
  5185   * load o(a),d
  5186   */
  5187  func (c *ctxt9) opload(a obj.As) uint32 {
  5188  	switch a {
  5189  	case AMOVD:
  5190  		return OPVCC(58, 0, 0, 0) /* ld */
  5191  	case AMOVDU:
  5192  		return OPVCC(58, 0, 0, 1) /* ldu */
  5193  	case AMOVWZ:
  5194  		return OPVCC(32, 0, 0, 0) /* lwz */
  5195  	case AMOVWZU:
  5196  		return OPVCC(33, 0, 0, 0) /* lwzu */
  5197  	case AMOVW:
  5198  		return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */
  5199  	case ALXV:
  5200  		return OPDQ(61, 1, 0) /* lxv - ISA v3.0 */
  5201  	case ALXVL:
  5202  		return OPVXX1(31, 269, 0) /* lxvl - ISA v3.0 */
  5203  	case ALXVLL:
  5204  		return OPVXX1(31, 301, 0) /* lxvll - ISA v3.0 */
  5205  	case ALXVX:
  5206  		return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
  5207  
  5208  		/* no AMOVWU */
  5209  	case AMOVB, AMOVBZ:
  5210  		return OPVCC(34, 0, 0, 0)
  5211  		/* load */
  5212  
  5213  	case AMOVBU, AMOVBZU:
  5214  		return OPVCC(35, 0, 0, 0)
  5215  	case AFMOVD:
  5216  		return OPVCC(50, 0, 0, 0)
  5217  	case AFMOVDU:
  5218  		return OPVCC(51, 0, 0, 0)
  5219  	case AFMOVS:
  5220  		return OPVCC(48, 0, 0, 0)
  5221  	case AFMOVSU:
  5222  		return OPVCC(49, 0, 0, 0)
  5223  	case AMOVH:
  5224  		return OPVCC(42, 0, 0, 0)
  5225  	case AMOVHU:
  5226  		return OPVCC(43, 0, 0, 0)
  5227  	case AMOVHZ:
  5228  		return OPVCC(40, 0, 0, 0)
  5229  	case AMOVHZU:
  5230  		return OPVCC(41, 0, 0, 0)
  5231  	case AMOVMW:
  5232  		return OPVCC(46, 0, 0, 0) /* lmw */
  5233  	}
  5234  
  5235  	c.ctxt.Diag("bad load opcode %v", a)
  5236  	return 0
  5237  }
  5238  
  5239  /*
  5240   * indexed load a(b),d
  5241   */
  5242  func (c *ctxt9) oploadx(a obj.As) uint32 {
  5243  	switch a {
  5244  	case AMOVWZ:
  5245  		return OPVCC(31, 23, 0, 0) /* lwzx */
  5246  	case AMOVWZU:
  5247  		return OPVCC(31, 55, 0, 0) /* lwzux */
  5248  	case AMOVW:
  5249  		return OPVCC(31, 341, 0, 0) /* lwax */
  5250  	case AMOVWU:
  5251  		return OPVCC(31, 373, 0, 0) /* lwaux */
  5252  
  5253  	case AMOVB, AMOVBZ:
  5254  		return OPVCC(31, 87, 0, 0) /* lbzx */
  5255  
  5256  	case AMOVBU, AMOVBZU:
  5257  		return OPVCC(31, 119, 0, 0) /* lbzux */
  5258  	case AFMOVD:
  5259  		return OPVCC(31, 599, 0, 0) /* lfdx */
  5260  	case AFMOVDU:
  5261  		return OPVCC(31, 631, 0, 0) /*  lfdux */
  5262  	case AFMOVS:
  5263  		return OPVCC(31, 535, 0, 0) /* lfsx */
  5264  	case AFMOVSU:
  5265  		return OPVCC(31, 567, 0, 0) /* lfsux */
  5266  	case AFMOVSX:
  5267  		return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */
  5268  	case AFMOVSZ:
  5269  		return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */
  5270  	case AMOVH:
  5271  		return OPVCC(31, 343, 0, 0) /* lhax */
  5272  	case AMOVHU:
  5273  		return OPVCC(31, 375, 0, 0) /* lhaux */
  5274  	case AMOVHBR:
  5275  		return OPVCC(31, 790, 0, 0) /* lhbrx */
  5276  	case AMOVWBR:
  5277  		return OPVCC(31, 534, 0, 0) /* lwbrx */
  5278  	case AMOVDBR:
  5279  		return OPVCC(31, 532, 0, 0) /* ldbrx */
  5280  	case AMOVHZ:
  5281  		return OPVCC(31, 279, 0, 0) /* lhzx */
  5282  	case AMOVHZU:
  5283  		return OPVCC(31, 311, 0, 0) /* lhzux */
  5284  	case ALBAR:
  5285  		return OPVCC(31, 52, 0, 0) /* lbarx */
  5286  	case ALHAR:
  5287  		return OPVCC(31, 116, 0, 0) /* lharx */
  5288  	case ALWAR:
  5289  		return OPVCC(31, 20, 0, 0) /* lwarx */
  5290  	case ALDAR:
  5291  		return OPVCC(31, 84, 0, 0) /* ldarx */
  5292  	case ALSW:
  5293  		return OPVCC(31, 533, 0, 0) /* lswx */
  5294  	case AMOVD:
  5295  		return OPVCC(31, 21, 0, 0) /* ldx */
  5296  	case AMOVDU:
  5297  		return OPVCC(31, 53, 0, 0) /* ldux */
  5298  
  5299  	/* Vector (VMX/Altivec) instructions */
  5300  	case ALVEBX:
  5301  		return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */
  5302  	case ALVEHX:
  5303  		return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */
  5304  	case ALVEWX:
  5305  		return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */
  5306  	case ALVX:
  5307  		return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */
  5308  	case ALVXL:
  5309  		return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */
  5310  	case ALVSL:
  5311  		return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */
  5312  	case ALVSR:
  5313  		return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */
  5314  		/* End of vector instructions */
  5315  
  5316  	/* Vector scalar (VSX) instructions */
  5317  	case ALXVX:
  5318  		return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
  5319  	case ALXVD2X:
  5320  		return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */
  5321  	case ALXVW4X:
  5322  		return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */
  5323  	case ALXVH8X:
  5324  		return OPVXX1(31, 812, 0) /* lxvh8x - v3.00 */
  5325  	case ALXVB16X:
  5326  		return OPVXX1(31, 876, 0) /* lxvb16x - v3.00 */
  5327  	case ALXVDSX:
  5328  		return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */
  5329  	case ALXSDX:
  5330  		return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */
  5331  	case ALXSIWAX:
  5332  		return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */
  5333  	case ALXSIWZX:
  5334  		return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */
  5335  	}
  5336  
  5337  	c.ctxt.Diag("bad loadx opcode %v", a)
  5338  	return 0
  5339  }
  5340  
  5341  /*
  5342   * store s,o(d)
  5343   */
  5344  func (c *ctxt9) opstore(a obj.As) uint32 {
  5345  	switch a {
  5346  	case AMOVB, AMOVBZ:
  5347  		return OPVCC(38, 0, 0, 0) /* stb */
  5348  
  5349  	case AMOVBU, AMOVBZU:
  5350  		return OPVCC(39, 0, 0, 0) /* stbu */
  5351  	case AFMOVD:
  5352  		return OPVCC(54, 0, 0, 0) /* stfd */
  5353  	case AFMOVDU:
  5354  		return OPVCC(55, 0, 0, 0) /* stfdu */
  5355  	case AFMOVS:
  5356  		return OPVCC(52, 0, 0, 0) /* stfs */
  5357  	case AFMOVSU:
  5358  		return OPVCC(53, 0, 0, 0) /* stfsu */
  5359  
  5360  	case AMOVHZ, AMOVH:
  5361  		return OPVCC(44, 0, 0, 0) /* sth */
  5362  
  5363  	case AMOVHZU, AMOVHU:
  5364  		return OPVCC(45, 0, 0, 0) /* sthu */
  5365  	case AMOVMW:
  5366  		return OPVCC(47, 0, 0, 0) /* stmw */
  5367  	case ASTSW:
  5368  		return OPVCC(31, 725, 0, 0) /* stswi */
  5369  
  5370  	case AMOVWZ, AMOVW:
  5371  		return OPVCC(36, 0, 0, 0) /* stw */
  5372  
  5373  	case AMOVWZU, AMOVWU:
  5374  		return OPVCC(37, 0, 0, 0) /* stwu */
  5375  	case AMOVD:
  5376  		return OPVCC(62, 0, 0, 0) /* std */
  5377  	case AMOVDU:
  5378  		return OPVCC(62, 0, 0, 1) /* stdu */
  5379  	case ASTXV:
  5380  		return OPDQ(61, 5, 0) /* stxv ISA 3.0 */
  5381  	case ASTXVL:
  5382  		return OPVXX1(31, 397, 0) /* stxvl ISA 3.0 */
  5383  	case ASTXVLL:
  5384  		return OPVXX1(31, 429, 0) /* stxvll ISA 3.0 */
  5385  	case ASTXVX:
  5386  		return OPVXX1(31, 396, 0) /* stxvx - ISA v3.0 */
  5387  
  5388  	}
  5389  
  5390  	c.ctxt.Diag("unknown store opcode %v", a)
  5391  	return 0
  5392  }
  5393  
  5394  /*
  5395   * indexed store s,a(b)
  5396   */
  5397  func (c *ctxt9) opstorex(a obj.As) uint32 {
  5398  	switch a {
  5399  	case AMOVB, AMOVBZ:
  5400  		return OPVCC(31, 215, 0, 0) /* stbx */
  5401  
  5402  	case AMOVBU, AMOVBZU:
  5403  		return OPVCC(31, 247, 0, 0) /* stbux */
  5404  	case AFMOVD:
  5405  		return OPVCC(31, 727, 0, 0) /* stfdx */
  5406  	case AFMOVDU:
  5407  		return OPVCC(31, 759, 0, 0) /* stfdux */
  5408  	case AFMOVS:
  5409  		return OPVCC(31, 663, 0, 0) /* stfsx */
  5410  	case AFMOVSU:
  5411  		return OPVCC(31, 695, 0, 0) /* stfsux */
  5412  	case AFMOVSX:
  5413  		return OPVCC(31, 983, 0, 0) /* stfiwx */
  5414  
  5415  	case AMOVHZ, AMOVH:
  5416  		return OPVCC(31, 407, 0, 0) /* sthx */
  5417  	case AMOVHBR:
  5418  		return OPVCC(31, 918, 0, 0) /* sthbrx */
  5419  
  5420  	case AMOVHZU, AMOVHU:
  5421  		return OPVCC(31, 439, 0, 0) /* sthux */
  5422  
  5423  	case AMOVWZ, AMOVW:
  5424  		return OPVCC(31, 151, 0, 0) /* stwx */
  5425  
  5426  	case AMOVWZU, AMOVWU:
  5427  		return OPVCC(31, 183, 0, 0) /* stwux */
  5428  	case ASTSW:
  5429  		return OPVCC(31, 661, 0, 0) /* stswx */
  5430  	case AMOVWBR:
  5431  		return OPVCC(31, 662, 0, 0) /* stwbrx */
  5432  	case AMOVDBR:
  5433  		return OPVCC(31, 660, 0, 0) /* stdbrx */
  5434  	case ASTBCCC:
  5435  		return OPVCC(31, 694, 0, 1) /* stbcx. */
  5436  	case ASTHCCC:
  5437  		return OPVCC(31, 726, 0, 1) /* sthcx. */
  5438  	case ASTWCCC:
  5439  		return OPVCC(31, 150, 0, 1) /* stwcx. */
  5440  	case ASTDCCC:
  5441  		return OPVCC(31, 214, 0, 1) /* stwdx. */
  5442  	case AMOVD:
  5443  		return OPVCC(31, 149, 0, 0) /* stdx */
  5444  	case AMOVDU:
  5445  		return OPVCC(31, 181, 0, 0) /* stdux */
  5446  
  5447  	/* Vector (VMX/Altivec) instructions */
  5448  	case ASTVEBX:
  5449  		return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */
  5450  	case ASTVEHX:
  5451  		return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */
  5452  	case ASTVEWX:
  5453  		return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */
  5454  	case ASTVX:
  5455  		return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */
  5456  	case ASTVXL:
  5457  		return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */
  5458  		/* End of vector instructions */
  5459  
  5460  	/* Vector scalar (VSX) instructions */
  5461  	case ASTXVX:
  5462  		return OPVXX1(31, 396, 0) /* stxvx - v3.0 */
  5463  	case ASTXVD2X:
  5464  		return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */
  5465  	case ASTXVW4X:
  5466  		return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */
  5467  	case ASTXVH8X:
  5468  		return OPVXX1(31, 940, 0) /* stxvh8x - v3.0 */
  5469  	case ASTXVB16X:
  5470  		return OPVXX1(31, 1004, 0) /* stxvb16x - v3.0 */
  5471  
  5472  	case ASTXSDX:
  5473  		return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */
  5474  
  5475  	case ASTXSIWX:
  5476  		return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */
  5477  
  5478  		/* End of vector scalar instructions */
  5479  
  5480  	}
  5481  
  5482  	c.ctxt.Diag("unknown storex opcode %v", a)
  5483  	return 0
  5484  }
  5485  

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