1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 package ppc64
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "encoding/binary"
36 "fmt"
37 "internal/buildcfg"
38 "log"
39 "math"
40 "math/bits"
41 "sort"
42 )
43
44
45
46
47 type ctxt9 struct {
48 ctxt *obj.Link
49 newprog obj.ProgAlloc
50 cursym *obj.LSym
51 autosize int32
52 instoffset int64
53 pc int64
54 }
55
56
57
58 const (
59 r0iszero = 1
60 )
61
62 const (
63
64 PFX_R_ABS = 0
65 PFX_R_PCREL = 1
66 )
67
68 const (
69
70 NOP = 0x60000000
71 )
72
73 type Optab struct {
74 as obj.As
75 a1 uint8
76 a2 uint8
77 a3 uint8
78 a4 uint8
79 a5 uint8
80 a6 uint8
81 type_ int8
82 size int8
83
84
85
86
87
88 ispfx bool
89
90 asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32)
91 }
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109 var optab []Optab
110
111 var optabBase = []Optab{
112 {as: obj.ATEXT, a1: C_LOREG, a6: C_TEXTSIZE, type_: 0, size: 0},
113 {as: obj.ATEXT, a1: C_LOREG, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
114 {as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE, type_: 0, size: 0},
115 {as: obj.ATEXT, a1: C_ADDR, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
116
117 {as: AADD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
118 {as: AADD, a1: C_REG, a6: C_REG, type_: 2, size: 4},
119 {as: AADD, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
120 {as: AADD, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
121 {as: AADD, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 22, size: 8},
122 {as: AADD, a1: C_U16CON, a6: C_REG, type_: 22, size: 8},
123 {as: AADDIS, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 20, size: 4},
124 {as: AADDIS, a1: C_S16CON, a6: C_REG, type_: 20, size: 4},
125 {as: AADDC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
126 {as: AADDC, a1: C_REG, a6: C_REG, type_: 2, size: 4},
127 {as: AADDC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
128 {as: AADDC, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
129 {as: AADDC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
130 {as: AADDC, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
131 {as: AAND, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
132 {as: AAND, a1: C_REG, a6: C_REG, type_: 6, size: 4},
133 {as: AANDCC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
134 {as: AANDCC, a1: C_REG, a6: C_REG, type_: 6, size: 4},
135 {as: AANDCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
136 {as: AANDCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
137 {as: AANDCC, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
138 {as: AANDCC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
139 {as: AANDCC, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
140 {as: AANDCC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
141 {as: AANDISCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
142 {as: AANDISCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
143 {as: AMULLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
144 {as: AMULLW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
145 {as: AMULLW, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
146 {as: AMULLW, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
147 {as: AMULLW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
148 {as: AMULLW, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
149 {as: ASUBC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
150 {as: ASUBC, a1: C_REG, a6: C_REG, type_: 10, size: 4},
151 {as: ASUBC, a1: C_REG, a3: C_S16CON, a6: C_REG, type_: 27, size: 4},
152 {as: ASUBC, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 28, size: 12},
153 {as: AOR, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
154 {as: AOR, a1: C_REG, a6: C_REG, type_: 6, size: 4},
155 {as: AOR, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
156 {as: AOR, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
157 {as: AOR, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
158 {as: AOR, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
159 {as: AOR, a1: C_U32CON, a2: C_REG, a6: C_REG, type_: 21, size: 8},
160 {as: AOR, a1: C_U32CON, a6: C_REG, type_: 21, size: 8},
161 {as: AOR, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
162 {as: AOR, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
163 {as: AORIS, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
164 {as: AORIS, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
165 {as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
166 {as: ADIVW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
167 {as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
168 {as: ASUB, a1: C_REG, a6: C_REG, type_: 10, size: 4},
169 {as: ASLW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
170 {as: ASLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
171 {as: ASLD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
172 {as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
173 {as: ASLD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
174 {as: ASLD, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
175 {as: AEXTSWSLI, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
176 {as: AEXTSWSLI, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
177 {as: ASLW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 57, size: 4},
178 {as: ASLW, a1: C_U15CON, a6: C_REG, type_: 57, size: 4},
179 {as: ASRAW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
180 {as: ASRAW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
181 {as: ASRAW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
182 {as: ASRAW, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
183 {as: ASRAD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
184 {as: ASRAD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
185 {as: ASRAD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
186 {as: ASRAD, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
187 {as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
188 {as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
189 {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
190 {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
191 {as: ACLRLSLWI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 62, size: 4},
192 {as: ARLDMI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 30, size: 4},
193 {as: ARLDC, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
194 {as: ARLDC, a1: C_REG, a3: C_U8CON, a4: C_U8CON, a6: C_REG, type_: 9, size: 4},
195 {as: ARLDCL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
196 {as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
197 {as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
198 {as: ARLDICL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
199 {as: ARLDCL, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
200 {as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4},
201 {as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4},
202 {as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
203 {as: AFABS, a6: C_FREG, type_: 33, size: 4},
204 {as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4},
205 {as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4},
206 {as: AFMUL, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 32, size: 4},
207
208 {as: AMOVBU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
209 {as: AMOVBU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
210 {as: AMOVBU, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
211 {as: AMOVBU, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
212
213 {as: AMOVBZU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
214 {as: AMOVBZU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
215 {as: AMOVBZU, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
216 {as: AMOVBZU, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
217
218 {as: AMOVHBR, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
219 {as: AMOVHBR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
220
221 {as: AMOVB, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
222 {as: AMOVB, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
223 {as: AMOVB, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
224 {as: AMOVB, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
225 {as: AMOVB, a1: C_REG, a6: C_REG, type_: 13, size: 4},
226
227 {as: AMOVBZ, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
228 {as: AMOVBZ, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
229 {as: AMOVBZ, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
230 {as: AMOVBZ, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
231 {as: AMOVBZ, a1: C_REG, a6: C_REG, type_: 13, size: 4},
232
233 {as: AMOVD, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
234 {as: AMOVD, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
235 {as: AMOVD, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
236 {as: AMOVD, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
237 {as: AMOVD, a1: C_SOREG, a6: C_SPR, type_: 107, size: 8},
238 {as: AMOVD, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
239 {as: AMOVD, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
240 {as: AMOVD, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
241 {as: AMOVD, a1: C_SPR, a6: C_SOREG, type_: 106, size: 8},
242 {as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
243 {as: AMOVD, a1: C_REG, a6: C_REG, type_: 13, size: 4},
244
245 {as: AMOVW, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
246 {as: AMOVW, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
247 {as: AMOVW, a1: C_CREG, a6: C_REG, type_: 68, size: 4},
248 {as: AMOVW, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
249 {as: AMOVW, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
250 {as: AMOVW, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
251 {as: AMOVW, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
252 {as: AMOVW, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
253 {as: AMOVW, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
254 {as: AMOVW, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
255 {as: AMOVW, a1: C_REG, a6: C_REG, type_: 13, size: 4},
256
257 {as: AFMOVD, a1: C_S16CON, a6: C_FREG, type_: 24, size: 8},
258 {as: AFMOVD, a1: C_SOREG, a6: C_FREG, type_: 8, size: 4},
259 {as: AFMOVD, a1: C_XOREG, a6: C_FREG, type_: 109, size: 4},
260 {as: AFMOVD, a1: C_ZCON, a6: C_FREG, type_: 24, size: 4},
261 {as: AFMOVD, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
262 {as: AFMOVD, a1: C_FREG, a6: C_SOREG, type_: 7, size: 4},
263 {as: AFMOVD, a1: C_FREG, a6: C_XOREG, type_: 108, size: 4},
264
265 {as: AFMOVSX, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
266 {as: AFMOVSX, a1: C_FREG, a6: C_XOREG, type_: 44, size: 4},
267
268 {as: AFMOVSZ, a1: C_ZOREG, a6: C_FREG, type_: 45, size: 4},
269 {as: AFMOVSZ, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
270
271 {as: AMOVFL, a1: C_CREG, a6: C_CREG, type_: 67, size: 4},
272 {as: AMOVFL, a1: C_FPSCR, a6: C_CREG, type_: 73, size: 4},
273 {as: AMOVFL, a1: C_FPSCR, a6: C_FREG, type_: 53, size: 4},
274 {as: AMOVFL, a1: C_FREG, a3: C_32CON, a6: C_FPSCR, type_: 64, size: 4},
275 {as: AMOVFL, a1: C_FREG, a6: C_FPSCR, type_: 64, size: 4},
276 {as: AMOVFL, a1: C_32CON, a6: C_FPSCR, type_: 65, size: 4},
277 {as: AMOVFL, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
278 {as: AMOVFL, a1: C_REG, a6: C_32CON, type_: 69, size: 4},
279
280 {as: ASYSCALL, type_: 5, size: 4},
281 {as: ASYSCALL, a1: C_REG, type_: 77, size: 12},
282 {as: ASYSCALL, a1: C_U15CON, type_: 77, size: 12},
283 {as: ABEQ, a6: C_BRA, type_: 16, size: 4},
284 {as: ABEQ, a1: C_CREG, a6: C_BRA, type_: 16, size: 4},
285 {as: ABR, a6: C_BRA, type_: 11, size: 4},
286 {as: ABR, a6: C_BRAPIC, type_: 11, size: 8},
287 {as: ABR, a6: C_LR, type_: 18, size: 4},
288 {as: ABR, a6: C_CTR, type_: 18, size: 4},
289 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_BRA, type_: 16, size: 4},
290 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_LR, type_: 18, size: 4},
291 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a3: C_U15CON, a6: C_LR, type_: 18, size: 4},
292 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_CTR, type_: 18, size: 4},
293 {as: ABDNZ, a6: C_BRA, type_: 16, size: 4},
294 {as: ASYNC, type_: 46, size: 4},
295 {as: AWORD, a1: C_32CON, type_: 40, size: 4},
296 {as: ADWORD, a1: C_64CON, type_: 31, size: 8},
297 {as: ADWORD, a1: C_LACON, type_: 31, size: 8},
298 {as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4},
299 {as: AEXTSB, a1: C_REG, a6: C_REG, type_: 48, size: 4},
300 {as: AEXTSB, a6: C_REG, type_: 48, size: 4},
301 {as: AISEL, a1: C_U5CON, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
302 {as: AISEL, a1: C_CRBIT, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
303 {as: ANEG, a1: C_REG, a6: C_REG, type_: 47, size: 4},
304 {as: ANEG, a6: C_REG, type_: 47, size: 4},
305 {as: AREM, a1: C_REG, a6: C_REG, type_: 50, size: 12},
306 {as: AREM, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 12},
307 {as: AREMU, a1: C_REG, a6: C_REG, type_: 50, size: 16},
308 {as: AREMU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 16},
309 {as: AREMD, a1: C_REG, a6: C_REG, type_: 51, size: 12},
310 {as: AREMD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 51, size: 12},
311 {as: AMTFSB0, a1: C_U15CON, type_: 52, size: 4},
312
313 {as: APOPCNTD, a1: C_REG, a6: C_REG, type_: 93, size: 4},
314 {as: ACMPB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 92, size: 4},
315 {as: ACMPEQB, a1: C_REG, a2: C_REG, a6: C_CREG, type_: 92, size: 4},
316 {as: ACMPEQB, a1: C_REG, a6: C_REG, type_: 70, size: 4},
317 {as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_U15CON, type_: 92, size: 4},
318 {as: AFTSQRT, a1: C_FREG, a6: C_U15CON, type_: 93, size: 4},
319 {as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4},
320 {as: ADARN, a1: C_U15CON, a6: C_REG, type_: 92, size: 4},
321 {as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4},
322 {as: AADDEX, a1: C_REG, a2: C_REG, a3: C_U15CON, a6: C_REG, type_: 94, size: 4},
323 {as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4},
324
325
326 {as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4},
327 {as: AVCLZLSBB, a1: C_VREG, a6: C_REG, type_: 85, size: 4},
328
329
330
331
332 {as: ALVEBX, a1: C_XOREG, a6: C_VREG, type_: 45, size: 4},
333
334
335 {as: ASTVEBX, a1: C_VREG, a6: C_XOREG, type_: 44, size: 4},
336
337
338 {as: AVAND, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
339 {as: AVOR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
340
341
342 {as: AVADDUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
343 {as: AVADDCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
344 {as: AVADDUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
345 {as: AVADDSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
346 {as: AVADDE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
347
348
349 {as: AVSUBUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
350 {as: AVSUBCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
351 {as: AVSUBUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
352 {as: AVSUBSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
353 {as: AVSUBE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
354
355
356 {as: AVMULESB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
357 {as: AVPMSUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
358 {as: AVMSUMUDM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
359
360
361 {as: AVR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
362
363
364 {as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
365 {as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
366 {as: AVSOI, a1: C_U16CON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
367
368
369 {as: AVCLZ, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
370 {as: AVPOPCNT, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
371
372
373 {as: AVCMPEQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
374 {as: AVCMPGT, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
375 {as: AVCMPNEZB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
376
377
378 {as: AVMRGOW, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
379
380
381 {as: AVPERM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
382
383
384 {as: AVBPERMQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
385
386
387 {as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
388
389
390 {as: AVSPLTB, a1: C_S16CON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
391 {as: AVSPLTISB, a1: C_S16CON, a6: C_VREG, type_: 82, size: 4},
392
393
394 {as: AVCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
395 {as: AVNCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
396 {as: AVSBOX, a1: C_VREG, a6: C_VREG, type_: 82, size: 4},
397
398
399 {as: AVSHASIGMA, a1: C_U16CON, a2: C_VREG, a3: C_U16CON, a6: C_VREG, type_: 82, size: 4},
400
401
402 {as: ALXVD2X, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
403 {as: ALXV, a1: C_SOREG, a6: C_VSREG, type_: 96, size: 4},
404 {as: ALXVL, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 98, size: 4},
405
406
407 {as: ASTXVD2X, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
408 {as: ASTXV, a1: C_VSREG, a6: C_SOREG, type_: 97, size: 4},
409 {as: ASTXVL, a1: C_VSREG, a2: C_REG, a6: C_REG, type_: 99, size: 4},
410
411
412 {as: ALXSDX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
413
414
415 {as: ASTXSDX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
416
417
418 {as: ALXSIWAX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
419
420
421 {as: ASTXSIWX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
422
423
424 {as: AMFVSRD, a1: C_VSREG, a6: C_REG, type_: 88, size: 4},
425 {as: AMFVSRD, a1: C_FREG, a6: C_REG, type_: 88, size: 4},
426
427
428 {as: AMTVSRD, a1: C_REG, a6: C_VSREG, type_: 104, size: 4},
429 {as: AMTVSRD, a1: C_REG, a6: C_FREG, type_: 104, size: 4},
430 {as: AMTVSRDD, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 104, size: 4},
431
432
433 {as: AXXLAND, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 90, size: 4},
434 {as: AXXLAND, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
435
436
437 {as: AXXSEL, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a6: C_VSREG, type_: 91, size: 4},
438
439
440 {as: AXXMRGHW, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
441
442
443 {as: AXXSPLTW, a1: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 89, size: 4},
444 {as: AXXSPLTIB, a1: C_U15CON, a6: C_VSREG, type_: 100, size: 4},
445
446
447 {as: AXXPERM, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
448
449
450 {as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 90, size: 4},
451
452
453 {as: AXXBRQ, a1: C_VSREG, a6: C_VSREG, type_: 101, size: 4},
454
455
456 {as: AXSCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
457
458
459 {as: AXVCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
460
461
462 {as: AXSCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
463
464
465 {as: AXSCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
466
467
468 {as: AXVCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
469
470
471 {as: AXVCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
472
473 {as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4},
474 {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
475 {as: ACMP, a1: C_REG, a6: C_S16CON, type_: 70, size: 4},
476 {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_S16CON, type_: 70, size: 4},
477 {as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4},
478 {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
479 {as: ACMPU, a1: C_REG, a6: C_U16CON, type_: 70, size: 4},
480 {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_U16CON, type_: 70, size: 4},
481 {as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4},
482 {as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4},
483 {as: ATW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 60, size: 4},
484 {as: ATW, a1: C_32CON, a2: C_REG, a6: C_S16CON, type_: 61, size: 4},
485 {as: ADCBF, a1: C_SOREG, type_: 43, size: 4},
486 {as: ADCBF, a1: C_XOREG, type_: 43, size: 4},
487 {as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_U15CON, type_: 43, size: 4},
488 {as: ADCBF, a1: C_SOREG, a6: C_U15CON, type_: 43, size: 4},
489 {as: ADCBF, a1: C_XOREG, a6: C_U15CON, type_: 43, size: 4},
490 {as: ASTDCCC, a1: C_REG, a2: C_REG, a6: C_XOREG, type_: 44, size: 4},
491 {as: ASTDCCC, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
492 {as: ALDAR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
493 {as: ALDAR, a1: C_XOREG, a3: C_U16CON, a6: C_REG, type_: 45, size: 4},
494 {as: AEIEIO, type_: 46, size: 4},
495 {as: ATLBIE, a1: C_REG, type_: 49, size: 4},
496 {as: ATLBIE, a1: C_U15CON, a6: C_REG, type_: 49, size: 4},
497 {as: ASLBMFEE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
498 {as: ASLBMTE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
499 {as: ASTSW, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
500 {as: ASTSW, a1: C_REG, a3: C_32CON, a6: C_ZOREG, type_: 41, size: 4},
501 {as: ALSW, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
502 {as: ALSW, a1: C_ZOREG, a3: C_32CON, a6: C_REG, type_: 42, size: 4},
503
504 {as: obj.AUNDEF, type_: 78, size: 4},
505 {as: obj.APCDATA, a1: C_32CON, a6: C_32CON, type_: 0, size: 0},
506 {as: obj.AFUNCDATA, a1: C_U15CON, a6: C_ADDR, type_: 0, size: 0},
507 {as: obj.ANOP, type_: 0, size: 0},
508 {as: obj.ANOP, a1: C_32CON, type_: 0, size: 0},
509 {as: obj.ANOP, a1: C_REG, type_: 0, size: 0},
510 {as: obj.ANOP, a1: C_FREG, type_: 0, size: 0},
511 {as: obj.ADUFFZERO, a6: C_BRA, type_: 11, size: 4},
512 {as: obj.ADUFFCOPY, a6: C_BRA, type_: 11, size: 4},
513 {as: obj.APCALIGN, a1: C_32CON, type_: 0, size: 0},
514 }
515
516
517
518 type PrefixableOptab struct {
519 Optab
520 minGOPPC64 int
521 pfxsize int8
522 }
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538 var prefixableOptab = []PrefixableOptab{
539 {Optab: Optab{as: AMOVD, a1: C_S34CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
540 {Optab: Optab{as: AMOVD, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
541 {Optab: Optab{as: AMOVD, a1: C_TLS_LE, a6: C_REG, type_: 79, size: 8}, minGOPPC64: 10, pfxsize: 8},
542 {Optab: Optab{as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 12}, minGOPPC64: 10, pfxsize: 12},
543 {Optab: Optab{as: AMOVD, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
544 {Optab: Optab{as: AMOVD, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
545 {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
546 {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
547
548 {Optab: Optab{as: AMOVW, a1: C_32CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
549 {Optab: Optab{as: AMOVW, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
550 {Optab: Optab{as: AMOVW, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
551 {Optab: Optab{as: AMOVW, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
552 {Optab: Optab{as: AMOVW, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
553 {Optab: Optab{as: AMOVW, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
554
555 {Optab: Optab{as: AMOVB, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
556 {Optab: Optab{as: AMOVB, a1: C_LOREG, a6: C_REG, type_: 36, size: 12}, minGOPPC64: 10, pfxsize: 12},
557 {Optab: Optab{as: AMOVB, a1: C_ADDR, a6: C_REG, type_: 75, size: 12}, minGOPPC64: 10, pfxsize: 12},
558 {Optab: Optab{as: AMOVB, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
559
560 {Optab: Optab{as: AMOVBZ, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
561 {Optab: Optab{as: AMOVBZ, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
562 {Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
563 {Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
564
565 {Optab: Optab{as: AFMOVD, a1: C_LOREG, a6: C_FREG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
566 {Optab: Optab{as: AFMOVD, a1: C_ADDR, a6: C_FREG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
567 {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
568 {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
569
570 {Optab: Optab{as: AADD, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
571 {Optab: Optab{as: AADD, a1: C_32CON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
572 {Optab: Optab{as: AADD, a1: C_S34CON, a2: C_REG, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
573 {Optab: Optab{as: AADD, a1: C_S34CON, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
574 }
575
576 var oprange [ALAST & obj.AMask][]Optab
577
578 var xcmp [C_NCLASS][C_NCLASS]bool
579
580 var pfxEnabled = false
581 var buildOpCfg = ""
582
583
584 func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
585 switch a {
586 case 8, 16, 32, 64:
587
588
589
590
591 if ctxt.Headtype != objabi.Haix && cursym.Func().Align < int32(a) {
592 cursym.Func().Align = int32(a)
593 }
594 if pc&(a-1) != 0 {
595 return int(a - (pc & (a - 1)))
596 }
597 default:
598 ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
599 }
600 return 0
601 }
602
603 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
604 p := cursym.Func().Text
605 if p == nil || p.Link == nil {
606 return
607 }
608
609 if oprange[AANDN&obj.AMask] == nil {
610 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
611 }
612
613 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
614
615 pc := int64(0)
616 p.Pc = pc
617
618 var m int
619 var o *Optab
620 for p = p.Link; p != nil; p = p.Link {
621 p.Pc = pc
622 o = c.oplook(p)
623 m = int(o.size)
624 if m == 0 {
625 if p.As == obj.APCALIGN {
626 a := c.vregoff(&p.From)
627 m = addpad(pc, a, ctxt, cursym)
628 } else {
629 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
630 ctxt.Diag("zero-width instruction\n%v", p)
631 }
632 continue
633 }
634 }
635 pc += int64(m)
636 }
637
638 c.cursym.Size = pc
639
640
646 bflag := 1
647
648 var otxt int64
649 var q *obj.Prog
650 var out [5]uint32
651 var falign int32
652 for bflag != 0 {
653 bflag = 0
654 pc = 0
655 falign = 0
656 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
657 p.Pc = pc
658 o = c.oplook(p)
659
660
661 if (o.type_ == 16 || o.type_ == 17) && p.To.Target() != nil {
662 otxt = p.To.Target().Pc - pc
663 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
664
665
666
667 tgt := p.To.Target()
668 p.To.SetTarget(p.Link)
669 o.asmout(&c, p, o, &out)
670 p.To.SetTarget(tgt)
671
672 bo := int64(out[0]>>21) & 31
673 bi := int16((out[0] >> 16) & 31)
674 invertible := false
675
676 if bo&0x14 == 0x14 {
677
678 } else if bo&0x10 == 0x10 {
679
680 bo ^= 0x2
681 invertible = true
682 } else if bo&0x04 == 0x04 {
683
684 bo ^= 0x8
685 invertible = true
686 }
687
688 if invertible {
689
690
691
692
693
694
695
696
697 p.As = ABC
698 p.From = obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: bo}
699 q = c.newprog()
700 q.As = ABR
701 q.To.Type = obj.TYPE_BRANCH
702 q.To.SetTarget(p.To.Target())
703 q.Link = p.Link
704 p.To.SetTarget(p.Link)
705 p.Link = q
706 p.Reg = REG_CRBIT0 + bi
707 } else {
708
709
710
711
712
713
714
715
716
717
718 q = c.newprog()
719 q.Link = p.Link
720 p.Link = q
721 q.As = ABR
722 q.To.Type = obj.TYPE_BRANCH
723 q.To.SetTarget(p.To.Target())
724 p.To.SetTarget(q)
725 q = c.newprog()
726 q.Link = p.Link
727 p.Link = q
728 q.As = ABR
729 q.To.Type = obj.TYPE_BRANCH
730 q.To.SetTarget(q.Link.Link)
731 }
732 bflag = 1
733 }
734 }
735
736 m = int(o.size)
737 if m == 0 {
738 if p.As == obj.APCALIGN {
739 a := c.vregoff(&p.From)
740 m = addpad(pc, a, ctxt, cursym)
741 } else {
742 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
743 ctxt.Diag("zero-width instruction\n%v", p)
744 }
745 continue
746 }
747 }
748
749
750
751
752 if o.ispfx {
753 mark := p.Mark &^ PFX_X64B
754 if pc&63 == 60 {
755 p.Pc += 4
756 m += 4
757 mark |= PFX_X64B
758 }
759
760
761
762
763
764
765 if mark != p.Mark {
766 bflag = 1
767 p.Mark = mark
768 }
769
770
771
772
773
774
775 switch p.Pc & 31 {
776 case 28:
777 falign = 64
778 case 12:
779 if falign < 64 {
780 falign = 32
781 }
782 }
783 }
784
785 pc += int64(m)
786 }
787
788 c.cursym.Size = pc
789 }
790
791 c.cursym.Size = pc
792 c.cursym.Func().Align = falign
793 c.cursym.Grow(c.cursym.Size)
794
795
796
797 bp := c.cursym.P
798 var i int32
799 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
800 c.pc = p.Pc
801 o = c.oplook(p)
802 if int(o.size) > 4*len(out) {
803 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
804 }
805
806 if o.type_ == 0 && p.As == obj.APCALIGN {
807 aln := c.vregoff(&p.From)
808 v := addpad(p.Pc, aln, c.ctxt, c.cursym)
809 if v > 0 {
810
811 for i = 0; i < int32(v/4); i++ {
812 c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
813 bp = bp[4:]
814 }
815 }
816 } else {
817 if p.Mark&PFX_X64B != 0 {
818 c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
819 bp = bp[4:]
820 }
821 o.asmout(&c, p, o, &out)
822 for i = 0; i < int32(o.size/4); i++ {
823 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
824 bp = bp[4:]
825 }
826 }
827 }
828 }
829
830 func isint32(v int64) bool {
831 return int64(int32(v)) == v
832 }
833
834 func isuint32(v uint64) bool {
835 return uint64(uint32(v)) == v
836 }
837
838 func (c *ctxt9) aclassreg(reg int16) int {
839 if REG_R0 <= reg && reg <= REG_R31 {
840 return C_REGP + int(reg&1)
841 }
842 if REG_F0 <= reg && reg <= REG_F31 {
843 return C_FREGP + int(reg&1)
844 }
845 if REG_V0 <= reg && reg <= REG_V31 {
846 return C_VREG
847 }
848 if REG_VS0 <= reg && reg <= REG_VS63 {
849 return C_VSREGP + int(reg&1)
850 }
851 if REG_CR0 <= reg && reg <= REG_CR7 || reg == REG_CR {
852 return C_CREG
853 }
854 if REG_CR0LT <= reg && reg <= REG_CR7SO {
855 return C_CRBIT
856 }
857 if REG_SPR0 <= reg && reg <= REG_SPR0+1023 {
858 switch reg {
859 case REG_LR:
860 return C_LR
861
862 case REG_CTR:
863 return C_CTR
864 }
865
866 return C_SPR
867 }
868 if REG_A0 <= reg && reg <= REG_A7 {
869 return C_AREG
870 }
871 if reg == REG_FPSCR {
872 return C_FPSCR
873 }
874 return C_GOK
875 }
876
877 func (c *ctxt9) aclass(a *obj.Addr) int {
878 switch a.Type {
879 case obj.TYPE_NONE:
880 return C_NONE
881
882 case obj.TYPE_REG:
883 return c.aclassreg(a.Reg)
884
885 case obj.TYPE_MEM:
886 if a.Index != 0 {
887 if a.Name != obj.NAME_NONE || a.Offset != 0 {
888 c.ctxt.Logf("Unexpected Instruction operand index %d offset %d class %d \n", a.Index, a.Offset, a.Class)
889
890 }
891 return C_XOREG
892 }
893 switch a.Name {
894 case obj.NAME_GOTREF, obj.NAME_TOCREF:
895 return C_ADDR
896
897 case obj.NAME_EXTERN,
898 obj.NAME_STATIC:
899 c.instoffset = a.Offset
900 if a.Sym == nil {
901 break
902 } else if a.Sym.Type == objabi.STLSBSS {
903
904 if c.ctxt.Flag_shared {
905 return C_TLS_IE
906 }
907
908 return C_TLS_LE
909 } else {
910 return C_ADDR
911 }
912
913 case obj.NAME_AUTO:
914 a.Reg = REGSP
915 c.instoffset = int64(c.autosize) + a.Offset
916 if c.instoffset >= -BIG && c.instoffset < BIG {
917 return C_SOREG
918 }
919 return C_LOREG
920
921 case obj.NAME_PARAM:
922 a.Reg = REGSP
923 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
924 if c.instoffset >= -BIG && c.instoffset < BIG {
925 return C_SOREG
926 }
927 return C_LOREG
928
929 case obj.NAME_NONE:
930 c.instoffset = a.Offset
931 if a.Offset == 0 && a.Index == 0 {
932 return C_ZOREG
933 } else if c.instoffset >= -BIG && c.instoffset < BIG {
934 return C_SOREG
935 } else {
936 return C_LOREG
937 }
938 }
939
940 return C_GOK
941
942 case obj.TYPE_TEXTSIZE:
943 return C_TEXTSIZE
944
945 case obj.TYPE_FCONST:
946
947
948 f64 := a.Val.(float64)
949 if f64 == 0 {
950 if math.Signbit(f64) {
951 return C_S16CON
952 }
953 return C_ZCON
954 }
955 log.Fatalf("Unexpected nonzero FCONST operand %v", a)
956
957 case obj.TYPE_CONST,
958 obj.TYPE_ADDR:
959 switch a.Name {
960 case obj.NAME_NONE:
961 c.instoffset = a.Offset
962 if a.Reg != 0 {
963 if -BIG <= c.instoffset && c.instoffset < BIG {
964 return C_SACON
965 }
966 if isint32(c.instoffset) {
967 return C_LACON
968 }
969 return C_DACON
970 }
971
972 case obj.NAME_EXTERN,
973 obj.NAME_STATIC:
974 s := a.Sym
975 if s == nil {
976 return C_GOK
977 }
978 c.instoffset = a.Offset
979 return C_LACON
980
981 case obj.NAME_AUTO:
982 a.Reg = REGSP
983 c.instoffset = int64(c.autosize) + a.Offset
984 if c.instoffset >= -BIG && c.instoffset < BIG {
985 return C_SACON
986 }
987 return C_LACON
988
989 case obj.NAME_PARAM:
990 a.Reg = REGSP
991 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
992 if c.instoffset >= -BIG && c.instoffset < BIG {
993 return C_SACON
994 }
995 return C_LACON
996
997 default:
998 return C_GOK
999 }
1000
1001 if c.instoffset >= 0 {
1002 sbits := bits.Len64(uint64(c.instoffset))
1003 switch {
1004 case sbits <= 5:
1005 return C_ZCON + sbits
1006 case sbits <= 8:
1007 return C_U8CON
1008 case sbits <= 15:
1009 return C_U15CON
1010 case sbits <= 16:
1011 return C_U16CON
1012 case sbits <= 31:
1013 return C_U31CON
1014 case sbits <= 32:
1015 return C_U32CON
1016 case sbits <= 33:
1017 return C_S34CON
1018 default:
1019 return C_64CON
1020 }
1021 } else {
1022 sbits := bits.Len64(uint64(^c.instoffset))
1023 switch {
1024 case sbits <= 15:
1025 return C_S16CON
1026 case sbits <= 31:
1027 return C_S32CON
1028 case sbits <= 33:
1029 return C_S34CON
1030 default:
1031 return C_64CON
1032 }
1033 }
1034
1035 case obj.TYPE_BRANCH:
1036 if a.Sym != nil && c.ctxt.Flag_dynlink && !pfxEnabled {
1037 return C_BRAPIC
1038 }
1039 return C_BRA
1040 }
1041
1042 return C_GOK
1043 }
1044
1045 func prasm(p *obj.Prog) {
1046 fmt.Printf("%v\n", p)
1047 }
1048
1049 func (c *ctxt9) oplook(p *obj.Prog) *Optab {
1050 a1 := int(p.Optab)
1051 if a1 != 0 {
1052 return &optab[a1-1]
1053 }
1054 a1 = int(p.From.Class)
1055 if a1 == 0 {
1056 a1 = c.aclass(&p.From) + 1
1057 p.From.Class = int8(a1)
1058 }
1059 a1--
1060
1061 argsv := [3]int{C_NONE + 1, C_NONE + 1, C_NONE + 1}
1062 for i, ap := range p.RestArgs {
1063 argsv[i] = int(ap.Addr.Class)
1064 if argsv[i] == 0 {
1065 argsv[i] = c.aclass(&ap.Addr) + 1
1066 ap.Addr.Class = int8(argsv[i])
1067 }
1068
1069 }
1070 a3 := argsv[0] - 1
1071 a4 := argsv[1] - 1
1072 a5 := argsv[2] - 1
1073
1074 a6 := int(p.To.Class)
1075 if a6 == 0 {
1076 a6 = c.aclass(&p.To) + 1
1077 p.To.Class = int8(a6)
1078 }
1079 a6--
1080
1081 a2 := C_NONE
1082 if p.Reg != 0 {
1083 a2 = c.aclassreg(p.Reg)
1084 }
1085
1086
1087 ops := oprange[p.As&obj.AMask]
1088 c1 := &xcmp[a1]
1089 c2 := &xcmp[a2]
1090 c3 := &xcmp[a3]
1091 c4 := &xcmp[a4]
1092 c5 := &xcmp[a5]
1093 c6 := &xcmp[a6]
1094 for i := range ops {
1095 op := &ops[i]
1096 if c1[op.a1] && c2[op.a2] && c3[op.a3] && c4[op.a4] && c5[op.a5] && c6[op.a6] {
1097 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1098 return op
1099 }
1100 }
1101
1102 c.ctxt.Diag("illegal combination %v %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5), DRconv(a6))
1103 prasm(p)
1104 if ops == nil {
1105 ops = optab
1106 }
1107 return &ops[0]
1108 }
1109
1110
1111
1112
1113
1114
1115
1116 func cmp(a int, b int) bool {
1117 if a == b {
1118 return true
1119 }
1120 switch a {
1121
1122 case C_SPR:
1123 if b == C_LR || b == C_CTR {
1124 return true
1125 }
1126
1127 case C_U1CON:
1128 return cmp(C_ZCON, b)
1129 case C_U2CON:
1130 return cmp(C_U1CON, b)
1131 case C_U3CON:
1132 return cmp(C_U2CON, b)
1133 case C_U4CON:
1134 return cmp(C_U3CON, b)
1135 case C_U5CON:
1136 return cmp(C_U4CON, b)
1137 case C_U8CON:
1138 return cmp(C_U5CON, b)
1139 case C_U15CON:
1140 return cmp(C_U8CON, b)
1141 case C_S16CON:
1142 return cmp(C_U15CON, b)
1143 case C_U16CON:
1144 return cmp(C_U15CON, b)
1145 case C_16CON:
1146 return cmp(C_S16CON, b) || cmp(C_U16CON, b)
1147 case C_U31CON:
1148 return cmp(C_U16CON, b)
1149 case C_U32CON:
1150 return cmp(C_U31CON, b)
1151 case C_S32CON:
1152 return cmp(C_U31CON, b) || cmp(C_S16CON, b)
1153 case C_32CON:
1154 return cmp(C_S32CON, b) || cmp(C_U32CON, b)
1155 case C_S34CON:
1156 return cmp(C_32CON, b)
1157 case C_64CON:
1158 return cmp(C_S34CON, b)
1159
1160 case C_LACON:
1161 return cmp(C_SACON, b)
1162
1163 case C_SOREG:
1164 return cmp(C_ZOREG, b)
1165
1166 case C_LOREG:
1167 return cmp(C_SOREG, b)
1168
1169 case C_XOREG:
1170 return cmp(C_REG, b) || cmp(C_ZOREG, b)
1171
1172
1173 case C_REG:
1174 return cmp(C_REGP, b) || (b == C_ZCON && r0iszero != 0)
1175 case C_FREG:
1176 return cmp(C_FREGP, b)
1177 case C_VSREG:
1178
1179 return cmp(C_VSREGP, b) || cmp(C_VREG, b)
1180
1181 case C_ANY:
1182 return true
1183 }
1184
1185 return false
1186 }
1187
1188
1189
1190
1191 func optabLess(i, j int) bool {
1192 p1 := &optab[i]
1193 p2 := &optab[j]
1194 n := int(p1.as) - int(p2.as)
1195
1196 if n != 0 {
1197 return n < 0
1198 }
1199
1200
1201 n = int(p1.size) - int(p2.size)
1202 if n != 0 {
1203 return n < 0
1204 }
1205
1206
1207 n = int(p1.a1) - int(p2.a1)
1208 if n != 0 {
1209 return n < 0
1210 }
1211 n = int(p1.a2) - int(p2.a2)
1212 if n != 0 {
1213 return n < 0
1214 }
1215 n = int(p1.a3) - int(p2.a3)
1216 if n != 0 {
1217 return n < 0
1218 }
1219 n = int(p1.a4) - int(p2.a4)
1220 if n != 0 {
1221 return n < 0
1222 }
1223 n = int(p1.a5) - int(p2.a5)
1224 if n != 0 {
1225 return n < 0
1226 }
1227 n = int(p1.a6) - int(p2.a6)
1228 if n != 0 {
1229 return n < 0
1230 }
1231 return false
1232 }
1233
1234
1235
1236
1237 func opset(a, b0 obj.As) {
1238 oprange[a&obj.AMask] = oprange[b0]
1239 }
1240
1241
1242
1243 func NeedTOCpointer(ctxt *obj.Link) bool {
1244 return !pfxEnabled && ctxt.Flag_shared
1245 }
1246
1247
1248 func buildop(ctxt *obj.Link) {
1249
1250 pfxEnabled = buildcfg.GOPPC64 >= 10 && buildcfg.GOOS == "linux"
1251 cfg := fmt.Sprintf("power%d/%s/%s", buildcfg.GOPPC64, buildcfg.GOARCH, buildcfg.GOOS)
1252 if cfg == buildOpCfg {
1253
1254
1255
1256 return
1257 }
1258 buildOpCfg = cfg
1259
1260
1261 prefixOptab := make([]Optab, 0, len(prefixableOptab))
1262 for _, entry := range prefixableOptab {
1263 entry := entry
1264 if pfxEnabled && buildcfg.GOPPC64 >= entry.minGOPPC64 {
1265
1266 entry.ispfx = true
1267 entry.size = entry.pfxsize
1268 }
1269 prefixOptab = append(prefixOptab, entry.Optab)
1270
1271 }
1272
1273 for i := 0; i < C_NCLASS; i++ {
1274 for n := 0; n < C_NCLASS; n++ {
1275 if cmp(n, i) {
1276 xcmp[i][n] = true
1277 }
1278 }
1279 }
1280
1281
1282 optab = make([]Optab, 0, len(optabBase)+len(optabGen)+len(prefixOptab))
1283 optab = append(optab, optabBase...)
1284 optab = append(optab, optabGen...)
1285 optab = append(optab, prefixOptab...)
1286 sort.Slice(optab, optabLess)
1287
1288 for i := range optab {
1289
1290 if optab[i].asmout == nil {
1291 optab[i].asmout = asmout
1292 }
1293 }
1294
1295 for i := 0; i < len(optab); {
1296 r := optab[i].as
1297 r0 := r & obj.AMask
1298 start := i
1299 for i < len(optab) && optab[i].as == r {
1300 i++
1301 }
1302 oprange[r0] = optab[start:i]
1303
1304 switch r {
1305 default:
1306 if !opsetGen(r) {
1307 ctxt.Diag("unknown op in build: %v", r)
1308 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
1309 }
1310
1311 case ADCBF:
1312 opset(ADCBI, r0)
1313
1314 opset(ADCBST, r0)
1315 opset(ADCBT, r0)
1316 opset(ADCBTST, r0)
1317 opset(ADCBZ, r0)
1318 opset(AICBI, r0)
1319
1320 case ASTDCCC:
1321 opset(ASTWCCC, r0)
1322 opset(ASTHCCC, r0)
1323 opset(ASTBCCC, r0)
1324
1325 case AREM:
1326 opset(AREM, r0)
1327
1328 case AREMU:
1329 opset(AREMU, r0)
1330
1331 case AREMD:
1332 opset(AREMDU, r0)
1333
1334 case AMULLW:
1335 opset(AMULLD, r0)
1336
1337 case ADIVW:
1338 opset(AMULHW, r0)
1339
1340 opset(AMULHWCC, r0)
1341 opset(AMULHWU, r0)
1342 opset(AMULHWUCC, r0)
1343 opset(AMULLWCC, r0)
1344 opset(AMULLWVCC, r0)
1345 opset(AMULLWV, r0)
1346 opset(ADIVWCC, r0)
1347 opset(ADIVWV, r0)
1348 opset(ADIVWVCC, r0)
1349 opset(ADIVWU, r0)
1350 opset(ADIVWUCC, r0)
1351 opset(ADIVWUV, r0)
1352 opset(ADIVWUVCC, r0)
1353 opset(AMODUD, r0)
1354 opset(AMODUW, r0)
1355 opset(AMODSD, r0)
1356 opset(AMODSW, r0)
1357 opset(AADDCC, r0)
1358 opset(AADDCV, r0)
1359 opset(AADDCVCC, r0)
1360 opset(AADDV, r0)
1361 opset(AADDVCC, r0)
1362 opset(AADDE, r0)
1363 opset(AADDECC, r0)
1364 opset(AADDEV, r0)
1365 opset(AADDEVCC, r0)
1366 opset(AMULHD, r0)
1367 opset(AMULHDCC, r0)
1368 opset(AMULHDU, r0)
1369 opset(AMULHDUCC, r0)
1370 opset(AMULLDCC, r0)
1371 opset(AMULLDVCC, r0)
1372 opset(AMULLDV, r0)
1373 opset(ADIVD, r0)
1374 opset(ADIVDCC, r0)
1375 opset(ADIVDE, r0)
1376 opset(ADIVDEU, r0)
1377 opset(ADIVDECC, r0)
1378 opset(ADIVDEUCC, r0)
1379 opset(ADIVDVCC, r0)
1380 opset(ADIVDV, r0)
1381 opset(ADIVDU, r0)
1382 opset(ADIVDUV, r0)
1383 opset(ADIVDUVCC, r0)
1384 opset(ADIVDUCC, r0)
1385
1386 case ACRAND:
1387 opset(ACRANDN, r0)
1388 opset(ACREQV, r0)
1389 opset(ACRNAND, r0)
1390 opset(ACRNOR, r0)
1391 opset(ACROR, r0)
1392 opset(ACRORN, r0)
1393 opset(ACRXOR, r0)
1394
1395 case APOPCNTD:
1396 opset(APOPCNTW, r0)
1397 opset(APOPCNTB, r0)
1398 opset(ACNTTZW, r0)
1399 opset(ACNTTZWCC, r0)
1400 opset(ACNTTZD, r0)
1401 opset(ACNTTZDCC, r0)
1402
1403 case ACOPY:
1404 opset(APASTECC, r0)
1405
1406 case AMADDHD:
1407 opset(AMADDHDU, r0)
1408 opset(AMADDLD, r0)
1409
1410 case AMOVBZ:
1411 opset(AMOVH, r0)
1412 opset(AMOVHZ, r0)
1413
1414 case AMOVBZU:
1415 opset(AMOVHU, r0)
1416
1417 opset(AMOVHZU, r0)
1418 opset(AMOVWU, r0)
1419 opset(AMOVWZU, r0)
1420 opset(AMOVDU, r0)
1421 opset(AMOVMW, r0)
1422
1423 case ALVEBX:
1424 opset(ALVEHX, r0)
1425 opset(ALVEWX, r0)
1426 opset(ALVX, r0)
1427 opset(ALVXL, r0)
1428 opset(ALVSL, r0)
1429 opset(ALVSR, r0)
1430
1431 case ASTVEBX:
1432 opset(ASTVEHX, r0)
1433 opset(ASTVEWX, r0)
1434 opset(ASTVX, r0)
1435 opset(ASTVXL, r0)
1436
1437 case AVAND:
1438 opset(AVAND, r0)
1439 opset(AVANDC, r0)
1440 opset(AVNAND, r0)
1441
1442 case AVMRGOW:
1443 opset(AVMRGEW, r0)
1444
1445 case AVOR:
1446 opset(AVOR, r0)
1447 opset(AVORC, r0)
1448 opset(AVXOR, r0)
1449 opset(AVNOR, r0)
1450 opset(AVEQV, r0)
1451
1452 case AVADDUM:
1453 opset(AVADDUBM, r0)
1454 opset(AVADDUHM, r0)
1455 opset(AVADDUWM, r0)
1456 opset(AVADDUDM, r0)
1457 opset(AVADDUQM, r0)
1458
1459 case AVADDCU:
1460 opset(AVADDCUQ, r0)
1461 opset(AVADDCUW, r0)
1462
1463 case AVADDUS:
1464 opset(AVADDUBS, r0)
1465 opset(AVADDUHS, r0)
1466 opset(AVADDUWS, r0)
1467
1468 case AVADDSS:
1469 opset(AVADDSBS, r0)
1470 opset(AVADDSHS, r0)
1471 opset(AVADDSWS, r0)
1472
1473 case AVADDE:
1474 opset(AVADDEUQM, r0)
1475 opset(AVADDECUQ, r0)
1476
1477 case AVSUBUM:
1478 opset(AVSUBUBM, r0)
1479 opset(AVSUBUHM, r0)
1480 opset(AVSUBUWM, r0)
1481 opset(AVSUBUDM, r0)
1482 opset(AVSUBUQM, r0)
1483
1484 case AVSUBCU:
1485 opset(AVSUBCUQ, r0)
1486 opset(AVSUBCUW, r0)
1487
1488 case AVSUBUS:
1489 opset(AVSUBUBS, r0)
1490 opset(AVSUBUHS, r0)
1491 opset(AVSUBUWS, r0)
1492
1493 case AVSUBSS:
1494 opset(AVSUBSBS, r0)
1495 opset(AVSUBSHS, r0)
1496 opset(AVSUBSWS, r0)
1497
1498 case AVSUBE:
1499 opset(AVSUBEUQM, r0)
1500 opset(AVSUBECUQ, r0)
1501
1502 case AVMULESB:
1503 opset(AVMULOSB, r0)
1504 opset(AVMULEUB, r0)
1505 opset(AVMULOUB, r0)
1506 opset(AVMULESH, r0)
1507 opset(AVMULOSH, r0)
1508 opset(AVMULEUH, r0)
1509 opset(AVMULOUH, r0)
1510 opset(AVMULESW, r0)
1511 opset(AVMULOSW, r0)
1512 opset(AVMULEUW, r0)
1513 opset(AVMULOUW, r0)
1514 opset(AVMULUWM, r0)
1515 case AVPMSUM:
1516 opset(AVPMSUMB, r0)
1517 opset(AVPMSUMH, r0)
1518 opset(AVPMSUMW, r0)
1519 opset(AVPMSUMD, r0)
1520
1521 case AVR:
1522 opset(AVRLB, r0)
1523 opset(AVRLH, r0)
1524 opset(AVRLW, r0)
1525 opset(AVRLD, r0)
1526
1527 case AVS:
1528 opset(AVSLB, r0)
1529 opset(AVSLH, r0)
1530 opset(AVSLW, r0)
1531 opset(AVSL, r0)
1532 opset(AVSLO, r0)
1533 opset(AVSRB, r0)
1534 opset(AVSRH, r0)
1535 opset(AVSRW, r0)
1536 opset(AVSR, r0)
1537 opset(AVSRO, r0)
1538 opset(AVSLD, r0)
1539 opset(AVSRD, r0)
1540
1541 case AVSA:
1542 opset(AVSRAB, r0)
1543 opset(AVSRAH, r0)
1544 opset(AVSRAW, r0)
1545 opset(AVSRAD, r0)
1546
1547 case AVSOI:
1548 opset(AVSLDOI, r0)
1549
1550 case AVCLZ:
1551 opset(AVCLZB, r0)
1552 opset(AVCLZH, r0)
1553 opset(AVCLZW, r0)
1554 opset(AVCLZD, r0)
1555
1556 case AVPOPCNT:
1557 opset(AVPOPCNTB, r0)
1558 opset(AVPOPCNTH, r0)
1559 opset(AVPOPCNTW, r0)
1560 opset(AVPOPCNTD, r0)
1561
1562 case AVCMPEQ:
1563 opset(AVCMPEQUB, r0)
1564 opset(AVCMPEQUBCC, r0)
1565 opset(AVCMPEQUH, r0)
1566 opset(AVCMPEQUHCC, r0)
1567 opset(AVCMPEQUW, r0)
1568 opset(AVCMPEQUWCC, r0)
1569 opset(AVCMPEQUD, r0)
1570 opset(AVCMPEQUDCC, r0)
1571
1572 case AVCMPGT:
1573 opset(AVCMPGTUB, r0)
1574 opset(AVCMPGTUBCC, r0)
1575 opset(AVCMPGTUH, r0)
1576 opset(AVCMPGTUHCC, r0)
1577 opset(AVCMPGTUW, r0)
1578 opset(AVCMPGTUWCC, r0)
1579 opset(AVCMPGTUD, r0)
1580 opset(AVCMPGTUDCC, r0)
1581 opset(AVCMPGTSB, r0)
1582 opset(AVCMPGTSBCC, r0)
1583 opset(AVCMPGTSH, r0)
1584 opset(AVCMPGTSHCC, r0)
1585 opset(AVCMPGTSW, r0)
1586 opset(AVCMPGTSWCC, r0)
1587 opset(AVCMPGTSD, r0)
1588 opset(AVCMPGTSDCC, r0)
1589
1590 case AVCMPNEZB:
1591 opset(AVCMPNEZBCC, r0)
1592 opset(AVCMPNEB, r0)
1593 opset(AVCMPNEBCC, r0)
1594 opset(AVCMPNEH, r0)
1595 opset(AVCMPNEHCC, r0)
1596 opset(AVCMPNEW, r0)
1597 opset(AVCMPNEWCC, r0)
1598
1599 case AVPERM:
1600 opset(AVPERMXOR, r0)
1601 opset(AVPERMR, r0)
1602
1603 case AVBPERMQ:
1604 opset(AVBPERMD, r0)
1605
1606 case AVSEL:
1607 opset(AVSEL, r0)
1608
1609 case AVSPLTB:
1610 opset(AVSPLTH, r0)
1611 opset(AVSPLTW, r0)
1612
1613 case AVSPLTISB:
1614 opset(AVSPLTISH, r0)
1615 opset(AVSPLTISW, r0)
1616
1617 case AVCIPH:
1618 opset(AVCIPHER, r0)
1619 opset(AVCIPHERLAST, r0)
1620
1621 case AVNCIPH:
1622 opset(AVNCIPHER, r0)
1623 opset(AVNCIPHERLAST, r0)
1624
1625 case AVSBOX:
1626 opset(AVSBOX, r0)
1627
1628 case AVSHASIGMA:
1629 opset(AVSHASIGMAW, r0)
1630 opset(AVSHASIGMAD, r0)
1631
1632 case ALXVD2X:
1633 opset(ALXVDSX, r0)
1634 opset(ALXVW4X, r0)
1635 opset(ALXVH8X, r0)
1636 opset(ALXVB16X, r0)
1637
1638 case ALXV:
1639 opset(ALXV, r0)
1640
1641 case ALXVL:
1642 opset(ALXVLL, r0)
1643 opset(ALXVX, r0)
1644
1645 case ASTXVD2X:
1646 opset(ASTXVW4X, r0)
1647 opset(ASTXVH8X, r0)
1648 opset(ASTXVB16X, r0)
1649
1650 case ASTXV:
1651 opset(ASTXV, r0)
1652
1653 case ASTXVL:
1654 opset(ASTXVLL, r0)
1655 opset(ASTXVX, r0)
1656
1657 case ALXSDX:
1658 opset(ALXSDX, r0)
1659
1660 case ASTXSDX:
1661 opset(ASTXSDX, r0)
1662
1663 case ALXSIWAX:
1664 opset(ALXSIWZX, r0)
1665
1666 case ASTXSIWX:
1667 opset(ASTXSIWX, r0)
1668
1669 case AMFVSRD:
1670 opset(AMFFPRD, r0)
1671 opset(AMFVRD, r0)
1672 opset(AMFVSRWZ, r0)
1673 opset(AMFVSRLD, r0)
1674
1675 case AMTVSRD:
1676 opset(AMTFPRD, r0)
1677 opset(AMTVRD, r0)
1678 opset(AMTVSRWA, r0)
1679 opset(AMTVSRWZ, r0)
1680 opset(AMTVSRWS, r0)
1681
1682 case AXXLAND:
1683 opset(AXXLANDC, r0)
1684 opset(AXXLEQV, r0)
1685 opset(AXXLNAND, r0)
1686 opset(AXXLORC, r0)
1687 opset(AXXLNOR, r0)
1688 opset(AXXLORQ, r0)
1689 opset(AXXLXOR, r0)
1690 opset(AXXLOR, r0)
1691 opset(AXSMAXJDP, r0)
1692 opset(AXSMINJDP, r0)
1693
1694 case AXXSEL:
1695 opset(AXXSEL, r0)
1696
1697 case AXXMRGHW:
1698 opset(AXXMRGLW, r0)
1699
1700 case AXXSPLTW:
1701 opset(AXXSPLTW, r0)
1702
1703 case AXXSPLTIB:
1704 opset(AXXSPLTIB, r0)
1705
1706 case AXXPERM:
1707 opset(AXXPERM, r0)
1708
1709 case AXXSLDWI:
1710 opset(AXXPERMDI, r0)
1711 opset(AXXSLDWI, r0)
1712
1713 case AXXBRQ:
1714 opset(AXXBRD, r0)
1715 opset(AXXBRW, r0)
1716 opset(AXXBRH, r0)
1717
1718 case AXSCVDPSP:
1719 opset(AXSCVSPDP, r0)
1720 opset(AXSCVDPSPN, r0)
1721 opset(AXSCVSPDPN, r0)
1722
1723 case AXVCVDPSP:
1724 opset(AXVCVSPDP, r0)
1725
1726 case AXSCVDPSXDS:
1727 opset(AXSCVDPSXWS, r0)
1728 opset(AXSCVDPUXDS, r0)
1729 opset(AXSCVDPUXWS, r0)
1730
1731 case AXSCVSXDDP:
1732 opset(AXSCVUXDDP, r0)
1733 opset(AXSCVSXDSP, r0)
1734 opset(AXSCVUXDSP, r0)
1735
1736 case AXVCVDPSXDS:
1737 opset(AXVCVDPSXDS, r0)
1738 opset(AXVCVDPSXWS, r0)
1739 opset(AXVCVDPUXDS, r0)
1740 opset(AXVCVDPUXWS, r0)
1741 opset(AXVCVSPSXDS, r0)
1742 opset(AXVCVSPSXWS, r0)
1743 opset(AXVCVSPUXDS, r0)
1744 opset(AXVCVSPUXWS, r0)
1745
1746 case AXVCVSXDDP:
1747 opset(AXVCVSXWDP, r0)
1748 opset(AXVCVUXDDP, r0)
1749 opset(AXVCVUXWDP, r0)
1750 opset(AXVCVSXDSP, r0)
1751 opset(AXVCVSXWSP, r0)
1752 opset(AXVCVUXDSP, r0)
1753 opset(AXVCVUXWSP, r0)
1754
1755 case AAND:
1756 opset(AANDN, r0)
1757 opset(AANDNCC, r0)
1758 opset(AEQV, r0)
1759 opset(AEQVCC, r0)
1760 opset(ANAND, r0)
1761 opset(ANANDCC, r0)
1762 opset(ANOR, r0)
1763 opset(ANORCC, r0)
1764 opset(AORCC, r0)
1765 opset(AORN, r0)
1766 opset(AORNCC, r0)
1767 opset(AXORCC, r0)
1768
1769 case AADDME:
1770 opset(AADDMECC, r0)
1771
1772 opset(AADDMEV, r0)
1773 opset(AADDMEVCC, r0)
1774 opset(AADDZE, r0)
1775 opset(AADDZECC, r0)
1776 opset(AADDZEV, r0)
1777 opset(AADDZEVCC, r0)
1778 opset(ASUBME, r0)
1779 opset(ASUBMECC, r0)
1780 opset(ASUBMEV, r0)
1781 opset(ASUBMEVCC, r0)
1782 opset(ASUBZE, r0)
1783 opset(ASUBZECC, r0)
1784 opset(ASUBZEV, r0)
1785 opset(ASUBZEVCC, r0)
1786
1787 case AADDC:
1788 opset(AADDCCC, r0)
1789
1790 case ABEQ:
1791 opset(ABGE, r0)
1792 opset(ABGT, r0)
1793 opset(ABLE, r0)
1794 opset(ABLT, r0)
1795 opset(ABNE, r0)
1796 opset(ABVC, r0)
1797 opset(ABVS, r0)
1798
1799 case ABR:
1800 opset(ABL, r0)
1801
1802 case ABC:
1803 opset(ABCL, r0)
1804
1805 case ABDNZ:
1806 opset(ABDZ, r0)
1807
1808 case AEXTSB:
1809 opset(AEXTSBCC, r0)
1810
1811 opset(AEXTSH, r0)
1812 opset(AEXTSHCC, r0)
1813 opset(ACNTLZW, r0)
1814 opset(ACNTLZWCC, r0)
1815 opset(ACNTLZD, r0)
1816 opset(AEXTSW, r0)
1817 opset(AEXTSWCC, r0)
1818 opset(ACNTLZDCC, r0)
1819
1820 case AFABS:
1821 opset(AFABSCC, r0)
1822
1823 opset(AFNABS, r0)
1824 opset(AFNABSCC, r0)
1825 opset(AFNEG, r0)
1826 opset(AFNEGCC, r0)
1827 opset(AFRSP, r0)
1828 opset(AFRSPCC, r0)
1829 opset(AFCTIW, r0)
1830 opset(AFCTIWCC, r0)
1831 opset(AFCTIWZ, r0)
1832 opset(AFCTIWZCC, r0)
1833 opset(AFCTID, r0)
1834 opset(AFCTIDCC, r0)
1835 opset(AFCTIDZ, r0)
1836 opset(AFCTIDZCC, r0)
1837 opset(AFCFID, r0)
1838 opset(AFCFIDCC, r0)
1839 opset(AFCFIDU, r0)
1840 opset(AFCFIDUCC, r0)
1841 opset(AFCFIDS, r0)
1842 opset(AFCFIDSCC, r0)
1843 opset(AFRES, r0)
1844 opset(AFRESCC, r0)
1845 opset(AFRIM, r0)
1846 opset(AFRIMCC, r0)
1847 opset(AFRIP, r0)
1848 opset(AFRIPCC, r0)
1849 opset(AFRIZ, r0)
1850 opset(AFRIZCC, r0)
1851 opset(AFRIN, r0)
1852 opset(AFRINCC, r0)
1853 opset(AFRSQRTE, r0)
1854 opset(AFRSQRTECC, r0)
1855 opset(AFSQRT, r0)
1856 opset(AFSQRTCC, r0)
1857 opset(AFSQRTS, r0)
1858 opset(AFSQRTSCC, r0)
1859
1860 case AFADD:
1861 opset(AFADDS, r0)
1862 opset(AFADDCC, r0)
1863 opset(AFADDSCC, r0)
1864 opset(AFCPSGN, r0)
1865 opset(AFCPSGNCC, r0)
1866 opset(AFDIV, r0)
1867 opset(AFDIVS, r0)
1868 opset(AFDIVCC, r0)
1869 opset(AFDIVSCC, r0)
1870 opset(AFSUB, r0)
1871 opset(AFSUBS, r0)
1872 opset(AFSUBCC, r0)
1873 opset(AFSUBSCC, r0)
1874
1875 case AFMADD:
1876 opset(AFMADDCC, r0)
1877 opset(AFMADDS, r0)
1878 opset(AFMADDSCC, r0)
1879 opset(AFMSUB, r0)
1880 opset(AFMSUBCC, r0)
1881 opset(AFMSUBS, r0)
1882 opset(AFMSUBSCC, r0)
1883 opset(AFNMADD, r0)
1884 opset(AFNMADDCC, r0)
1885 opset(AFNMADDS, r0)
1886 opset(AFNMADDSCC, r0)
1887 opset(AFNMSUB, r0)
1888 opset(AFNMSUBCC, r0)
1889 opset(AFNMSUBS, r0)
1890 opset(AFNMSUBSCC, r0)
1891 opset(AFSEL, r0)
1892 opset(AFSELCC, r0)
1893
1894 case AFMUL:
1895 opset(AFMULS, r0)
1896 opset(AFMULCC, r0)
1897 opset(AFMULSCC, r0)
1898
1899 case AFCMPO:
1900 opset(AFCMPU, r0)
1901
1902 case AMTFSB0:
1903 opset(AMTFSB0CC, r0)
1904 opset(AMTFSB1, r0)
1905 opset(AMTFSB1CC, r0)
1906
1907 case ANEG:
1908 opset(ANEGCC, r0)
1909
1910 opset(ANEGV, r0)
1911 opset(ANEGVCC, r0)
1912
1913 case AOR:
1914 opset(AXOR, r0)
1915
1916 case AORIS:
1917 opset(AXORIS, r0)
1918
1919 case ASLW:
1920 opset(ASLWCC, r0)
1921 opset(ASRW, r0)
1922 opset(ASRWCC, r0)
1923 opset(AROTLW, r0)
1924
1925 case ASLD:
1926 opset(ASLDCC, r0)
1927 opset(ASRD, r0)
1928 opset(ASRDCC, r0)
1929 opset(AROTL, r0)
1930
1931 case ASRAW:
1932 opset(ASRAWCC, r0)
1933
1934 case AEXTSWSLI:
1935 opset(AEXTSWSLICC, r0)
1936
1937 case ASRAD:
1938 opset(ASRADCC, r0)
1939
1940 case ASUB:
1941 opset(ASUB, r0)
1942
1943 opset(ASUBCC, r0)
1944 opset(ASUBV, r0)
1945 opset(ASUBVCC, r0)
1946 opset(ASUBCCC, r0)
1947 opset(ASUBCV, r0)
1948 opset(ASUBCVCC, r0)
1949 opset(ASUBE, r0)
1950 opset(ASUBECC, r0)
1951 opset(ASUBEV, r0)
1952 opset(ASUBEVCC, r0)
1953
1954 case ASYNC:
1955 opset(AISYNC, r0)
1956 opset(ALWSYNC, r0)
1957 opset(APTESYNC, r0)
1958 opset(ATLBSYNC, r0)
1959
1960 case ARLWNM:
1961 opset(ARLWNMCC, r0)
1962 opset(ARLWMI, r0)
1963 opset(ARLWMICC, r0)
1964
1965 case ARLDMI:
1966 opset(ARLDMICC, r0)
1967 opset(ARLDIMI, r0)
1968 opset(ARLDIMICC, r0)
1969
1970 case ARLDC:
1971 opset(ARLDCCC, r0)
1972
1973 case ARLDCL:
1974 opset(ARLDCR, r0)
1975 opset(ARLDCLCC, r0)
1976 opset(ARLDCRCC, r0)
1977
1978 case ARLDICL:
1979 opset(ARLDICLCC, r0)
1980 opset(ARLDICR, r0)
1981 opset(ARLDICRCC, r0)
1982 opset(ARLDIC, r0)
1983 opset(ARLDICCC, r0)
1984 opset(ACLRLSLDI, r0)
1985
1986 case AFMOVD:
1987 opset(AFMOVDCC, r0)
1988 opset(AFMOVDU, r0)
1989 opset(AFMOVS, r0)
1990 opset(AFMOVSU, r0)
1991
1992 case ALDAR:
1993 opset(ALBAR, r0)
1994 opset(ALHAR, r0)
1995 opset(ALWAR, r0)
1996
1997 case ASYSCALL:
1998 opset(ARFI, r0)
1999
2000 opset(ARFCI, r0)
2001 opset(ARFID, r0)
2002 opset(AHRFID, r0)
2003
2004 case AMOVHBR:
2005 opset(AMOVWBR, r0)
2006 opset(AMOVDBR, r0)
2007
2008 case ASLBMFEE:
2009 opset(ASLBMFEV, r0)
2010
2011 case ATW:
2012 opset(ATD, r0)
2013
2014 case ATLBIE:
2015 opset(ASLBIE, r0)
2016 opset(ATLBIEL, r0)
2017
2018 case AEIEIO:
2019 opset(ASLBIA, r0)
2020
2021 case ACMP:
2022 opset(ACMPW, r0)
2023
2024 case ACMPU:
2025 opset(ACMPWU, r0)
2026
2027 case ACMPB:
2028 opset(ACMPB, r0)
2029
2030 case AFTDIV:
2031 opset(AFTDIV, r0)
2032
2033 case AFTSQRT:
2034 opset(AFTSQRT, r0)
2035
2036 case AMOVW:
2037 opset(AMOVWZ, r0)
2038
2039 case AVCLZLSBB:
2040 opset(AVCTZLSBB, r0)
2041
2042 case AADD,
2043 AADDIS,
2044 AANDCC,
2045 AANDISCC,
2046 AFMOVSX,
2047 AFMOVSZ,
2048 ALSW,
2049 AMOVD,
2050 AMOVB,
2051 AMOVBU,
2052 AMOVFL,
2053
2054 ASUBC,
2055 ASTSW,
2056 ASLBMTE,
2057 AWORD,
2058 ADWORD,
2059 ADARN,
2060 AVMSUMUDM,
2061 AADDEX,
2062 ACMPEQB,
2063 ACLRLSLWI,
2064 AMTVSRDD,
2065 APNOP,
2066 AISEL,
2067 ASETB,
2068 obj.ANOP,
2069 obj.ATEXT,
2070 obj.AUNDEF,
2071 obj.AFUNCDATA,
2072 obj.APCALIGN,
2073 obj.APCDATA,
2074 obj.ADUFFZERO,
2075 obj.ADUFFCOPY:
2076 break
2077 }
2078 }
2079 }
2080
2081 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
2082 return o<<26 | xo<<1 | oe<<11
2083 }
2084
2085 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
2086 return o<<26 | xo<<2 | oe<<11
2087 }
2088
2089 func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32 {
2090 return o<<26 | xo<<2 | oe<<16
2091 }
2092
2093 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
2094 return o<<26 | xo<<3 | oe<<11
2095 }
2096
2097 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
2098 return o<<26 | xo<<4 | oe<<11
2099 }
2100
2101 func OPDQ(o uint32, xo uint32, oe uint32) uint32 {
2102 return o<<26 | xo | oe<<4
2103 }
2104
2105 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2106 return o<<26 | xo | oe<<11 | rc&1
2107 }
2108
2109 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2110 return o<<26 | xo | oe<<11 | (rc&1)<<10
2111 }
2112
2113 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2114 return o<<26 | xo<<1 | oe<<10 | rc&1
2115 }
2116
2117 func OPCC(o uint32, xo uint32, rc uint32) uint32 {
2118 return OPVCC(o, xo, 0, rc)
2119 }
2120
2121
2122 func OPMD(o, xo, rc uint32) uint32 {
2123 return o<<26 | xo<<2 | rc&1
2124 }
2125
2126
2127 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
2128 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
2129 }
2130
2131
2132 func AOP_RR(op uint32, d uint32, a uint32) uint32 {
2133 return op | (d&31)<<21 | (a&31)<<11
2134 }
2135
2136
2137 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2138 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
2139 }
2140
2141 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2142 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
2143 }
2144
2145
2146 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2147 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
2148 }
2149
2150
2151 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
2152 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
2153 }
2154
2155
2156 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
2157 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
2158 }
2159
2160
2161 func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
2162 return op | (d&31)<<21 | (simm&31)<<16
2163 }
2164
2165
2166 func AOP_XX1(op uint32, r uint32, a uint32, b uint32) uint32 {
2167 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
2168 }
2169
2170
2171 func AOP_XX2(op uint32, xt uint32, a uint32, xb uint32) uint32 {
2172 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
2173 }
2174
2175
2176 func AOP_XX3(op uint32, xt uint32, xa uint32, xb uint32) uint32 {
2177 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2178 }
2179
2180
2181 func AOP_XX3I(op uint32, xt uint32, xa uint32, xb uint32, c uint32) uint32 {
2182 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2183 }
2184
2185
2186 func AOP_XX4(op uint32, xt uint32, xa uint32, xb uint32, xc uint32) uint32 {
2187 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2188 }
2189
2190
2191 func AOP_DQ(op uint32, xt uint32, a uint32, b uint32) uint32 {
2192
2193
2194
2195
2196
2197
2198 dq := b >> 4
2199 return op | (xt&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (xt&32)>>2
2200 }
2201
2202
2203 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2204 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<9
2205 }
2206
2207
2208 func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2209 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
2210 }
2211
2212 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
2213 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
2214 }
2215
2216 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
2217 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
2218 }
2219
2220 func OP_BR(op uint32, li uint32, aa uint32) uint32 {
2221 return op | li&0x03FFFFFC | aa<<1
2222 }
2223
2224 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
2225 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
2226 }
2227
2228 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
2229 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
2230 }
2231
2232 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
2233 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
2234 }
2235
2236 func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32 {
2237 return op | (a&31)<<21 | (s&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1
2238 }
2239
2240 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
2241 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
2242 }
2243
2244
2245 func AOP_MD(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
2246 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
2247 }
2248
2249
2250 func AOP_MDS(op, to, from, rsh, m uint32) uint32 {
2251 return AOP_MD(op, to, from, rsh&31, m)
2252 }
2253
2254 func AOP_PFX_00_8LS(r, ie uint32) uint32 {
2255 return 1<<26 | 0<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
2256 }
2257 func AOP_PFX_10_MLS(r, ie uint32) uint32 {
2258 return 1<<26 | 2<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
2259 }
2260
2261 const (
2262
2263 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
2264 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
2265 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
2266 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0
2267 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0
2268 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0
2269 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0
2270 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0
2271 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0
2272 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0
2273 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
2274 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
2275 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
2276 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
2277 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
2278 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
2279 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
2280 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
2281 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
2282 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
2283 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
2284 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
2285 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0
2286 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0
2287 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0
2288 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0
2289 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0
2290 OP_XORI = 26<<26 | 0<<1 | 0<<10 | 0
2291 OP_XORIS = 27<<26 | 0<<1 | 0<<10 | 0
2292 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
2293 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0
2294 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0
2295 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0
2296 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
2297 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
2298 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0
2299 OP_EXTSWSLI = 31<<26 | 445<<2
2300 OP_SETB = 31<<26 | 128<<1
2301 )
2302
2303 func pfxadd(rt, ra int16, r uint32, imm32 int64) (uint32, uint32) {
2304 return AOP_PFX_10_MLS(r, uint32(imm32>>16)), AOP_IRR(14<<26, uint32(rt), uint32(ra), uint32(imm32))
2305 }
2306
2307 func pfxload(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
2308 switch a {
2309 case AMOVH:
2310 return AOP_PFX_10_MLS(r, 0), AOP_IRR(42<<26, uint32(reg), uint32(base), 0)
2311 case AMOVW:
2312 return AOP_PFX_00_8LS(r, 0), AOP_IRR(41<<26, uint32(reg), uint32(base), 0)
2313 case AMOVD:
2314 return AOP_PFX_00_8LS(r, 0), AOP_IRR(57<<26, uint32(reg), uint32(base), 0)
2315 case AMOVBZ, AMOVB:
2316 return AOP_PFX_10_MLS(r, 0), AOP_IRR(34<<26, uint32(reg), uint32(base), 0)
2317 case AMOVHZ:
2318 return AOP_PFX_10_MLS(r, 0), AOP_IRR(40<<26, uint32(reg), uint32(base), 0)
2319 case AMOVWZ:
2320 return AOP_PFX_10_MLS(r, 0), AOP_IRR(32<<26, uint32(reg), uint32(base), 0)
2321 case AFMOVS:
2322 return AOP_PFX_10_MLS(r, 0), AOP_IRR(48<<26, uint32(reg), uint32(base), 0)
2323 case AFMOVD:
2324 return AOP_PFX_10_MLS(r, 0), AOP_IRR(50<<26, uint32(reg), uint32(base), 0)
2325 }
2326 log.Fatalf("Error no pfxload for %v\n", a)
2327 return 0, 0
2328 }
2329
2330 func pfxstore(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
2331 switch a {
2332 case AMOVD:
2333 return AOP_PFX_00_8LS(r, 0), AOP_IRR(61<<26, uint32(reg), uint32(base), 0)
2334 case AMOVBZ, AMOVB:
2335 return AOP_PFX_10_MLS(r, 0), AOP_IRR(38<<26, uint32(reg), uint32(base), 0)
2336 case AMOVHZ, AMOVH:
2337 return AOP_PFX_10_MLS(r, 0), AOP_IRR(44<<26, uint32(reg), uint32(base), 0)
2338 case AMOVWZ, AMOVW:
2339 return AOP_PFX_10_MLS(r, 0), AOP_IRR(36<<26, uint32(reg), uint32(base), 0)
2340 case AFMOVS:
2341 return AOP_PFX_10_MLS(r, 0), AOP_IRR(52<<26, uint32(reg), uint32(base), 0)
2342 case AFMOVD:
2343 return AOP_PFX_10_MLS(r, 0), AOP_IRR(54<<26, uint32(reg), uint32(base), 0)
2344 }
2345 log.Fatalf("Error no pfxstore for %v\n", a)
2346 return 0, 0
2347 }
2348
2349 func oclass(a *obj.Addr) int {
2350 return int(a.Class) - 1
2351 }
2352
2353 const (
2354 D_FORM = iota
2355 DS_FORM
2356 )
2357
2358
2359
2360
2361
2362
2363
2364
2365 func (c *ctxt9) opform(insn uint32) int {
2366 switch insn {
2367 default:
2368 c.ctxt.Diag("bad insn in loadform: %x", insn)
2369 case OPVCC(58, 0, 0, 0),
2370 OPVCC(58, 0, 0, 1),
2371 OPVCC(58, 0, 0, 0) | 1<<1,
2372 OPVCC(62, 0, 0, 0),
2373 OPVCC(62, 0, 0, 1):
2374 return DS_FORM
2375 case OP_ADDI,
2376 OPVCC(32, 0, 0, 0),
2377 OPVCC(33, 0, 0, 0),
2378 OPVCC(34, 0, 0, 0),
2379 OPVCC(35, 0, 0, 0),
2380 OPVCC(40, 0, 0, 0),
2381 OPVCC(41, 0, 0, 0),
2382 OPVCC(42, 0, 0, 0),
2383 OPVCC(43, 0, 0, 0),
2384 OPVCC(46, 0, 0, 0),
2385 OPVCC(48, 0, 0, 0),
2386 OPVCC(49, 0, 0, 0),
2387 OPVCC(50, 0, 0, 0),
2388 OPVCC(51, 0, 0, 0),
2389 OPVCC(36, 0, 0, 0),
2390 OPVCC(37, 0, 0, 0),
2391 OPVCC(38, 0, 0, 0),
2392 OPVCC(39, 0, 0, 0),
2393 OPVCC(44, 0, 0, 0),
2394 OPVCC(45, 0, 0, 0),
2395 OPVCC(47, 0, 0, 0),
2396 OPVCC(52, 0, 0, 0),
2397 OPVCC(53, 0, 0, 0),
2398 OPVCC(54, 0, 0, 0),
2399 OPVCC(55, 0, 0, 0):
2400 return D_FORM
2401 }
2402 return 0
2403 }
2404
2405
2406
2407 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32, reuse bool) (o1, o2 uint32, rel *obj.Reloc) {
2408 if c.ctxt.Headtype == objabi.Haix {
2409
2410 c.ctxt.Diag("symbolAccess called for %s", s.Name)
2411 }
2412 var base uint32
2413 form := c.opform(op)
2414 if c.ctxt.Flag_shared {
2415 base = REG_R2
2416 } else {
2417 base = REG_R0
2418 }
2419
2420
2421 if !reuse {
2422 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
2423 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
2424 } else {
2425 o1 = AOP_IRR(OP_ADDIS, uint32(reg), base, 0)
2426 o2 = AOP_IRR(op, uint32(reg), uint32(reg), 0)
2427 }
2428 rel = obj.Addrel(c.cursym)
2429 rel.Off = int32(c.pc)
2430 rel.Siz = 8
2431 rel.Sym = s
2432 rel.Add = d
2433 if c.ctxt.Flag_shared {
2434 switch form {
2435 case D_FORM:
2436 rel.Type = objabi.R_ADDRPOWER_TOCREL
2437 case DS_FORM:
2438 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
2439 }
2440
2441 } else {
2442 switch form {
2443 case D_FORM:
2444 rel.Type = objabi.R_ADDRPOWER
2445 case DS_FORM:
2446 rel.Type = objabi.R_ADDRPOWER_DS
2447 }
2448 }
2449 return
2450 }
2451
2452
2453
2454
2455
2456
2457 func decodeMask32(mask uint32) (mb, me uint32, valid bool) {
2458 mb = uint32(bits.LeadingZeros32(mask))
2459 me = uint32(32 - bits.TrailingZeros32(mask))
2460 mbn := uint32(bits.LeadingZeros32(^mask))
2461 men := uint32(32 - bits.TrailingZeros32(^mask))
2462
2463 if mb == 0 && me == 32 {
2464
2465 mb, me = men, mbn
2466 }
2467
2468
2469
2470 v := mask
2471 vp := (v & -v) + v
2472
2473 vn := ^v
2474 vpn := (vn & -vn) + vn
2475 return mb, (me - 1) & 31, (v&vp == 0 || vn&vpn == 0) && v != 0
2476 }
2477
2478
2479
2480
2481
2482
2483
2484
2485 func decodeMask64(mask int64) (mb, me uint32, valid bool) {
2486 m := uint64(mask)
2487 mb = uint32(bits.LeadingZeros64(m))
2488 me = uint32(64 - bits.TrailingZeros64(m))
2489 valid = ((m&-m)+m)&m == 0 && m != 0
2490 return mb, (me - 1) & 63, valid
2491 }
2492
2493
2494 func loadl16(r int, d int64) uint32 {
2495 v := uint16(d)
2496 if v == 0 {
2497
2498
2499 return NOP
2500 }
2501 return LOP_IRR(OP_ORI, uint32(r), uint32(r), uint32(v))
2502 }
2503
2504
2505 func loadu32(r int, d int64) uint32 {
2506 v := int32(d >> 16)
2507 if isuint32(uint64(d)) {
2508 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
2509 }
2510 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
2511 }
2512
2513 func high16adjusted(d int32) uint16 {
2514 if d&0x8000 != 0 {
2515 return uint16((d >> 16) + 1)
2516 }
2517 return uint16(d >> 16)
2518 }
2519
2520 func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
2521 o1 := uint32(0)
2522 o2 := uint32(0)
2523 o3 := uint32(0)
2524 o4 := uint32(0)
2525 o5 := uint32(0)
2526
2527
2528 switch o.type_ {
2529 default:
2530 c.ctxt.Diag("unknown type %d", o.type_)
2531 prasm(p)
2532
2533 case 0:
2534 break
2535
2536 case 2:
2537 r := int(p.Reg)
2538
2539 if r == 0 {
2540 r = int(p.To.Reg)
2541 }
2542 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2543
2544 case 3:
2545 d := c.vregoff(&p.From)
2546
2547 v := int32(d)
2548 r := int(p.From.Reg)
2549
2550 if r0iszero != 0 && p.To.Reg == 0 && (r != 0 || v != 0) {
2551 c.ctxt.Diag("literal operation on R0\n%v", p)
2552 }
2553 if int64(int16(d)) == d {
2554
2555 o1 = AOP_IRR(uint32(OP_ADDI), uint32(p.To.Reg), uint32(r), uint32(v))
2556 } else {
2557
2558 if int64(uint16(d)) != d || (r != 0 && r != REGZERO) {
2559 c.ctxt.Diag("Rule expects a uint16 constant load. got:\n%v", p)
2560 }
2561 o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
2562 }
2563
2564 case 4:
2565 v := c.regoff(&p.From)
2566
2567 r := int(p.Reg)
2568 if r == 0 {
2569 r = int(p.To.Reg)
2570 }
2571 if r0iszero != 0 && p.To.Reg == 0 {
2572 c.ctxt.Diag("literal operation on R0\n%v", p)
2573 }
2574 if int32(int16(v)) != v {
2575 log.Fatalf("mishandled instruction %v", p)
2576 }
2577 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2578
2579 case 5:
2580 o1 = c.oprrr(p.As)
2581
2582 case 6:
2583 r := int(p.Reg)
2584
2585 if r == 0 {
2586 r = int(p.To.Reg)
2587 }
2588
2589 switch p.As {
2590 case AROTL:
2591 o1 = AOP_MD(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
2592 case AROTLW:
2593 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
2594 default:
2595 if p.As == AOR && p.From.Type == obj.TYPE_CONST && p.From.Offset == 0 {
2596
2597
2598 o1 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(r), 0)
2599 } else {
2600 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2601 }
2602 }
2603
2604 case 7:
2605 r := int(p.To.Reg)
2606 v := c.regoff(&p.To)
2607 if int32(int16(v)) != v {
2608 log.Fatalf("mishandled instruction %v", p)
2609 }
2610
2611 inst := c.opstore(p.As)
2612 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2613 log.Fatalf("invalid offset for DS form load/store %v", p)
2614 }
2615 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
2616
2617 case 8:
2618 r := int(p.From.Reg)
2619 v := c.regoff(&p.From)
2620 if int32(int16(v)) != v {
2621 log.Fatalf("mishandled instruction %v", p)
2622 }
2623
2624 inst := c.opload(p.As)
2625 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2626 log.Fatalf("invalid offset for DS form load/store %v", p)
2627 }
2628 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
2629
2630
2631 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
2632
2633 case 9:
2634 sh := uint32(p.RestArgs[0].Addr.Offset) & 0x3F
2635 mb := uint32(p.RestArgs[1].Addr.Offset) & 0x3F
2636 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), (uint32(sh) & 0x1F))
2637 o1 |= (sh & 0x20) >> 4
2638 o1 |= (mb & 0x1F) << 6
2639 o1 |= (mb & 0x20)
2640
2641 case 10:
2642 r := int(p.Reg)
2643
2644 if r == 0 {
2645 r = int(p.To.Reg)
2646 }
2647 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
2648
2649 case 11:
2650 v := int32(0)
2651
2652 if p.To.Target() != nil {
2653 v = int32(p.To.Target().Pc - p.Pc)
2654 if v&03 != 0 {
2655 c.ctxt.Diag("odd branch target address\n%v", p)
2656 v &^= 03
2657 }
2658
2659 if v < -(1<<25) || v >= 1<<24 {
2660 c.ctxt.Diag("branch too far\n%v", p)
2661 }
2662 }
2663
2664 o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
2665 if p.To.Sym != nil {
2666 rel := obj.Addrel(c.cursym)
2667 rel.Off = int32(c.pc)
2668 rel.Siz = 4
2669 rel.Sym = p.To.Sym
2670 v += int32(p.To.Offset)
2671 if v&03 != 0 {
2672 c.ctxt.Diag("odd branch target address\n%v", p)
2673 v &^= 03
2674 }
2675
2676 rel.Add = int64(v)
2677 rel.Type = objabi.R_CALLPOWER
2678 }
2679 o2 = NOP
2680
2681 case 13:
2682
2683
2684
2685 if p.From.Type == obj.TYPE_CONST {
2686 o1 = LOP_IRR(OP_ADDI, REGZERO, uint32(p.To.Reg), 0)
2687 break
2688 }
2689 if p.To.Type == obj.TYPE_CONST {
2690 c.ctxt.Diag("cannot move into constant 0\n%v", p)
2691 }
2692
2693 switch p.As {
2694 case AMOVB:
2695 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2696 case AMOVBZ:
2697 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
2698 case AMOVH:
2699 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2700 case AMOVHZ:
2701 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
2702 case AMOVW:
2703 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2704 case AMOVWZ:
2705 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5
2706 case AMOVD:
2707 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
2708 default:
2709 c.ctxt.Diag("internal: bad register move/truncation\n%v", p)
2710 }
2711
2712 case 14:
2713 r := uint32(p.Reg)
2714
2715 if r == 0 {
2716 r = uint32(p.To.Reg)
2717 }
2718 d := c.vregoff(p.GetFrom3())
2719 switch p.As {
2720
2721
2722
2723
2724 case ARLDCL, ARLDCLCC:
2725 mb, me, valid := decodeMask64(d)
2726 if me != 63 || !valid {
2727 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
2728 }
2729 o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), mb)
2730
2731 case ARLDCR, ARLDCRCC:
2732 mb, me, valid := decodeMask64(d)
2733 if mb != 0 || !valid {
2734 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p)
2735 }
2736 o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), me)
2737
2738
2739 case ARLDICR, ARLDICRCC:
2740 me := uint32(d)
2741 sh := c.regoff(&p.From)
2742 if me < 0 || me > 63 || sh > 63 {
2743 c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh, p)
2744 }
2745 o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), me)
2746
2747 case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
2748 mb := uint32(d)
2749 sh := c.regoff(&p.From)
2750 if mb < 0 || mb > 63 || sh > 63 {
2751 c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh, p)
2752 }
2753 o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), mb)
2754
2755 case ACLRLSLDI:
2756
2757
2758
2759
2760 n := int32(d)
2761 b := c.regoff(&p.From)
2762 if n > b || b > 63 {
2763 c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b, p)
2764 }
2765 o1 = AOP_MD(OP_RLDIC, uint32(p.To.Reg), uint32(r), uint32(n), uint32(b)-uint32(n))
2766
2767 default:
2768 c.ctxt.Diag("unexpected op in rldc case\n%v", p)
2769 }
2770
2771 case 16:
2772 a := 0
2773
2774 r := int(p.Reg)
2775
2776 if p.From.Type == obj.TYPE_CONST {
2777 a = int(c.regoff(&p.From))
2778 } else if p.From.Type == obj.TYPE_REG {
2779 if r != 0 {
2780 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
2781 }
2782
2783 switch p.From.Reg {
2784 case REG_CR0:
2785 r = BI_CR0
2786 case REG_CR1:
2787 r = BI_CR1
2788 case REG_CR2:
2789 r = BI_CR2
2790 case REG_CR3:
2791 r = BI_CR3
2792 case REG_CR4:
2793 r = BI_CR4
2794 case REG_CR5:
2795 r = BI_CR5
2796 case REG_CR6:
2797 r = BI_CR6
2798 case REG_CR7:
2799 r = BI_CR7
2800 default:
2801 c.ctxt.Diag("unrecognized register: expecting CR\n")
2802 }
2803 }
2804 v := int32(0)
2805 if p.To.Target() != nil {
2806 v = int32(p.To.Target().Pc - p.Pc)
2807 }
2808 if v&03 != 0 {
2809 c.ctxt.Diag("odd branch target address\n%v", p)
2810 v &^= 03
2811 }
2812
2813 if v < -(1<<16) || v >= 1<<15 {
2814 c.ctxt.Diag("branch too far\n%v", p)
2815 }
2816 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
2817
2818 case 18:
2819 var v int32
2820 var bh uint32 = 0
2821 if p.As == ABC || p.As == ABCL {
2822 v = c.regoff(&p.From) & 31
2823 } else {
2824 v = 20
2825 }
2826 r := int(p.Reg)
2827 if r == 0 {
2828 r = 0
2829 }
2830 switch oclass(&p.To) {
2831 case C_CTR:
2832 o1 = OPVCC(19, 528, 0, 0)
2833
2834 case C_LR:
2835 o1 = OPVCC(19, 16, 0, 0)
2836
2837 default:
2838 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
2839 v = 0
2840 }
2841
2842
2843 if p.From3Type() != obj.TYPE_NONE {
2844 bh = uint32(p.GetFrom3().Offset)
2845 if bh == 2 || bh > 3 {
2846 log.Fatalf("BH must be 0,1,3 for %v", p)
2847 }
2848 o1 |= bh << 11
2849 }
2850
2851 if p.As == ABL || p.As == ABCL {
2852 o1 |= 1
2853 }
2854 o1 = OP_BCR(o1, uint32(v), uint32(r))
2855
2856 case 19:
2857 d := c.vregoff(&p.From)
2858 if o.ispfx {
2859 o1, o2 = pfxadd(p.To.Reg, REG_R0, PFX_R_ABS, d)
2860 } else {
2861 o1 = loadu32(int(p.To.Reg), d)
2862 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
2863 }
2864
2865 case 20:
2866 v := c.regoff(&p.From)
2867
2868 r := int(p.Reg)
2869 if r == 0 {
2870 r = int(p.To.Reg)
2871 }
2872 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2873
2874 case 21:
2875 var opu, opl uint32
2876 r := uint32(p.Reg)
2877 if r == 0 {
2878 r = uint32(p.To.Reg)
2879 }
2880 switch p.As {
2881 case AOR:
2882 opu, opl = OP_ORIS, OP_ORI
2883 case AXOR:
2884 opu, opl = OP_XORIS, OP_XORI
2885 default:
2886 c.ctxt.Diag("unhandled opcode.\n%v", p)
2887 }
2888 o1 = LOP_IRR(opu, uint32(p.To.Reg), r, uint32(p.From.Offset>>16))
2889 o2 = LOP_IRR(opl, uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.From.Offset)&0xFFFF)
2890
2891 case 22:
2892 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2893 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2894 }
2895 d := c.vregoff(&p.From)
2896 r := int(p.Reg)
2897 if r == 0 {
2898 r = int(p.To.Reg)
2899 }
2900 if p.From.Sym != nil {
2901 c.ctxt.Diag("%v is not supported", p)
2902 }
2903 if o.ispfx {
2904 o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, d)
2905 } else if o.size == 8 {
2906 o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))
2907 o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2908 } else if o.size == 12 {
2909
2910 o1 = loadu32(REGTMP, d)
2911 o2 = loadl16(REGTMP, d)
2912 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2913 } else {
2914
2915 o1 = LOP_IRR(OP_ADDIS, REGZERO, REGTMP, uint32(d>>32))
2916 o2 = loadl16(REGTMP, int64(d>>16))
2917 o3 = AOP_MD(OP_RLDICR, REGTMP, REGTMP, 16, 63-16)
2918 o4 = loadl16(REGTMP, int64(uint16(d)))
2919 o5 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2920 }
2921
2922 case 23:
2923 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2924 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2925 }
2926 d := c.vregoff(&p.From)
2927 r := int(p.Reg)
2928 if r == 0 {
2929 r = int(p.To.Reg)
2930 }
2931
2932
2933
2934 if o.size == 8 {
2935 o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
2936 o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2937 } else {
2938 o1 = loadu32(REGTMP, d)
2939 o2 = loadl16(REGTMP, d)
2940 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2941 }
2942 if p.From.Sym != nil {
2943 c.ctxt.Diag("%v is not supported", p)
2944 }
2945
2946 case 24:
2947 o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
2948
2949 if o.size == 8 {
2950 o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
2951 }
2952
2953 case 25:
2954
2955 v := c.regoff(&p.From)
2956
2957 if v < 0 {
2958 v = 0
2959 } else if v > 63 {
2960 v = 63
2961 }
2962 r := int(p.Reg)
2963 if r == 0 {
2964 r = int(p.To.Reg)
2965 }
2966 var a int
2967 op := uint32(0)
2968 switch p.As {
2969 case ASLD, ASLDCC:
2970 a = int(63 - v)
2971 op = OP_RLDICR
2972
2973 case ASRD, ASRDCC:
2974 a = int(v)
2975 v = 64 - v
2976 op = OP_RLDICL
2977 case AROTL:
2978 a = int(0)
2979 op = OP_RLDICL
2980 case AEXTSWSLI, AEXTSWSLICC:
2981 a = int(v)
2982 default:
2983 c.ctxt.Diag("unexpected op in sldi case\n%v", p)
2984 a = 0
2985 o1 = 0
2986 }
2987
2988 if p.As == AEXTSWSLI || p.As == AEXTSWSLICC {
2989 o1 = AOP_EXTSWSLI(OP_EXTSWSLI, uint32(r), uint32(p.To.Reg), uint32(v))
2990
2991 } else {
2992 o1 = AOP_MD(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
2993 }
2994 if p.As == ASLDCC || p.As == ASRDCC || p.As == AEXTSWSLICC {
2995 o1 |= 1
2996 }
2997
2998 case 26:
2999 v := c.vregoff(&p.From)
3000 r := int(p.From.Reg)
3001 var rel *obj.Reloc
3002
3003 switch p.From.Name {
3004 case obj.NAME_EXTERN, obj.NAME_STATIC:
3005
3006 o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI, true)
3007 default:
3008
3009 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(int32(v))))
3010 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3011 }
3012
3013 if o.ispfx {
3014 if rel == nil {
3015 o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, v)
3016 } else {
3017 o1, o2 = pfxadd(int16(p.To.Reg), REG_R0, PFX_R_PCREL, 0)
3018 rel.Type = objabi.R_ADDRPOWER_PCREL34
3019 }
3020 }
3021
3022 case 27:
3023 v := c.regoff(p.GetFrom3())
3024
3025 r := int(p.From.Reg)
3026 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3027
3028 case 28:
3029 if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
3030 c.ctxt.Diag("can't synthesize large constant\n%v", p)
3031 }
3032 v := c.vregoff(p.GetFrom3())
3033 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
3034 o2 = loadl16(REGTMP, v)
3035 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
3036 if p.From.Sym != nil {
3037 c.ctxt.Diag("%v is not supported", p)
3038 }
3039
3040 case 29:
3041 sh := uint32(c.regoff(&p.From))
3042 d := c.vregoff(p.GetFrom3())
3043 mb, me, valid := decodeMask64(d)
3044 var a uint32
3045 switch p.As {
3046 case ARLDC, ARLDCCC:
3047 a = mb
3048 if me != (63-sh) || !valid {
3049 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3050 }
3051
3052 case ARLDCL, ARLDCLCC:
3053 a = mb
3054 if mb != 63 || !valid {
3055 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3056 }
3057
3058 case ARLDCR, ARLDCRCC:
3059 a = me
3060 if mb != 0 || !valid {
3061 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3062 }
3063
3064 default:
3065 c.ctxt.Diag("unexpected op in rldic case\n%v", p)
3066 }
3067 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, a)
3068
3069 case 30:
3070 sh := uint32(c.regoff(&p.From))
3071 d := c.vregoff(p.GetFrom3())
3072
3073
3074
3075 switch p.As {
3076 case ARLDMI, ARLDMICC:
3077 mb, me, valid := decodeMask64(d)
3078 if me != (63-sh) || !valid {
3079 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), me, sh, p)
3080 }
3081 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, mb)
3082
3083
3084 case ARLDIMI, ARLDIMICC:
3085 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, uint32(d))
3086 }
3087
3088 case 31:
3089 d := c.vregoff(&p.From)
3090
3091 if c.ctxt.Arch.ByteOrder == binary.BigEndian {
3092 o1 = uint32(d >> 32)
3093 o2 = uint32(d)
3094 } else {
3095 o1 = uint32(d)
3096 o2 = uint32(d >> 32)
3097 }
3098
3099 if p.From.Sym != nil {
3100 rel := obj.Addrel(c.cursym)
3101 rel.Off = int32(c.pc)
3102 rel.Siz = 8
3103 rel.Sym = p.From.Sym
3104 rel.Add = p.From.Offset
3105 rel.Type = objabi.R_ADDR
3106 o2 = 0
3107 o1 = o2
3108 }
3109
3110 case 32:
3111 r := int(p.Reg)
3112
3113 if r == 0 {
3114 r = int(p.To.Reg)
3115 }
3116 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
3117
3118 case 33:
3119 r := int(p.From.Reg)
3120
3121 if oclass(&p.From) == C_NONE {
3122 r = int(p.To.Reg)
3123 }
3124 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
3125
3126 case 34:
3127 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
3128
3129 case 35:
3130 v := c.regoff(&p.To)
3131 r := int(p.To.Reg)
3132
3133 if o.ispfx {
3134 o1, o2 = pfxstore(p.As, p.From.Reg, int16(r), PFX_R_ABS)
3135 o1 |= uint32((v >> 16) & 0x3FFFF)
3136 o2 |= uint32(v & 0xFFFF)
3137 } else {
3138 inst := c.opstore(p.As)
3139 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3140 log.Fatalf("invalid offset for DS form load/store %v", p)
3141 }
3142 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
3143 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
3144 }
3145
3146 case 36:
3147 v := c.regoff(&p.From)
3148 r := int(p.From.Reg)
3149
3150 if o.ispfx {
3151 o1, o2 = pfxload(p.As, p.To.Reg, int16(r), PFX_R_ABS)
3152 o1 |= uint32((v >> 16) & 0x3FFFF)
3153 o2 |= uint32(v & 0xFFFF)
3154 } else {
3155 if o.a6 == C_REG {
3156
3157
3158 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
3159 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3160 } else {
3161 o1 = AOP_IRR(OP_ADDIS, uint32(REGTMP), uint32(r), uint32(high16adjusted(v)))
3162 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(REGTMP), uint32(v))
3163 }
3164 }
3165
3166
3167 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3168
3169 case 40:
3170 o1 = uint32(c.regoff(&p.From))
3171
3172 case 41:
3173 if p.To.Type == obj.TYPE_MEM && p.To.Index == 0 && p.To.Offset != 0 {
3174 c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
3175 }
3176
3177 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3178
3179 case 42:
3180 if p.From.Type == obj.TYPE_MEM && p.From.Index == 0 && p.From.Offset != 0 {
3181 c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
3182 }
3183 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3184
3185 case 43:
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196 if p.To.Type == obj.TYPE_NONE {
3197 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
3198 } else {
3199 th := c.regoff(&p.To)
3200 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
3201 }
3202
3203 case 44:
3204 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3205
3206 case 45:
3207 switch p.As {
3208
3209
3210
3211
3212 case ALBAR, ALHAR, ALWAR, ALDAR:
3213 if p.From3Type() != obj.TYPE_NONE {
3214 eh := int(c.regoff(p.GetFrom3()))
3215 if eh > 1 {
3216 c.ctxt.Diag("illegal EH field\n%v", p)
3217 }
3218 o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
3219 } else {
3220 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3221 }
3222 default:
3223 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3224 }
3225 case 46:
3226 o1 = c.oprrr(p.As)
3227
3228 case 47:
3229 r := int(p.From.Reg)
3230
3231 if r == 0 {
3232 r = int(p.To.Reg)
3233 }
3234 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3235
3236 case 48:
3237 r := int(p.From.Reg)
3238
3239 if r == 0 {
3240 r = int(p.To.Reg)
3241 }
3242 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3243
3244 case 49:
3245 if p.From.Type != obj.TYPE_REG {
3246 v := c.regoff(&p.From) & 1
3247 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
3248 } else {
3249 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
3250 }
3251
3252 case 50:
3253 r := int(p.Reg)
3254
3255 if r == 0 {
3256 r = int(p.To.Reg)
3257 }
3258 v := c.oprrr(p.As)
3259 t := v & (1<<10 | 1)
3260 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3261 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
3262 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3263 if p.As == AREMU {
3264 o4 = o3
3265
3266
3267 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
3268 }
3269
3270 case 51:
3271 r := int(p.Reg)
3272
3273 if r == 0 {
3274 r = int(p.To.Reg)
3275 }
3276 v := c.oprrr(p.As)
3277 t := v & (1<<10 | 1)
3278 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3279 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
3280 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3281
3282
3283
3284
3285 case 52:
3286 v := c.regoff(&p.From) & 31
3287
3288 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
3289
3290 case 53:
3291 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
3292
3293 case 55:
3294 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
3295
3296 case 56:
3297 v := c.regoff(&p.From)
3298
3299 r := int(p.Reg)
3300 if r == 0 {
3301 r = int(p.To.Reg)
3302 }
3303 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
3304 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
3305 o1 |= 1 << 1
3306 }
3307
3308 case 57:
3309 v := c.regoff(&p.From)
3310
3311 r := int(p.Reg)
3312 if r == 0 {
3313 r = int(p.To.Reg)
3314 }
3315
3316
3323 if v < 0 {
3324 v = 0
3325 } else if v > 32 {
3326 v = 32
3327 }
3328 var mask [2]uint8
3329 switch p.As {
3330 case AROTLW:
3331 mask[0], mask[1] = 0, 31
3332 case ASRW, ASRWCC:
3333 mask[0], mask[1] = uint8(v), 31
3334 v = 32 - v
3335 default:
3336 mask[0], mask[1] = 0, uint8(31-v)
3337 }
3338 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
3339 if p.As == ASLWCC || p.As == ASRWCC {
3340 o1 |= 1
3341 }
3342
3343 case 58:
3344 v := c.regoff(&p.From)
3345
3346 r := int(p.Reg)
3347 if r == 0 {
3348 r = int(p.To.Reg)
3349 }
3350 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3351
3352 case 60:
3353 r := int(c.regoff(&p.From) & 31)
3354
3355 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
3356
3357 case 61:
3358 r := int(c.regoff(&p.From) & 31)
3359
3360 v := c.regoff(&p.To)
3361 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
3362
3363 case 62:
3364 v := c.regoff(&p.From)
3365 n := c.regoff(p.GetFrom3())
3366
3367
3368
3369 if n > v || v >= 32 {
3370 c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, n, p)
3371 }
3372
3373 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(n), uint32(v-n), uint32(31-n))
3374
3375 case 63:
3376 var mb, me uint32
3377 if len(p.RestArgs) == 1 {
3378 var valid bool
3379
3380 mb, me, valid = decodeMask32(uint32(p.RestArgs[0].Addr.Offset))
3381 if !valid {
3382 c.ctxt.Diag("cannot generate mask #%x\n%v", uint64(p.RestArgs[0].Addr.Offset), p)
3383 }
3384 } else {
3385 mb, me = uint32(p.RestArgs[0].Addr.Offset), uint32(p.RestArgs[1].Addr.Offset)
3386 }
3387 if p.From.Type == obj.TYPE_CONST {
3388 o1 = OP_RLW(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Offset), mb, me)
3389 } else {
3390 o1 = OP_RLW(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), mb, me)
3391 }
3392
3393 case 64:
3394 var v int32
3395 if p.From3Type() != obj.TYPE_NONE {
3396 v = c.regoff(p.GetFrom3()) & 255
3397 } else {
3398 v = 255
3399 }
3400 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
3401
3402 case 65:
3403 if p.To.Reg == 0 {
3404 c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
3405 }
3406 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
3407
3408 case 66:
3409 var r int
3410 var v int32
3411 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
3412 r = int(p.From.Reg)
3413 v = int32(p.To.Reg)
3414 o1 = OPVCC(31, 467, 0, 0)
3415 } else {
3416 r = int(p.To.Reg)
3417 v = int32(p.From.Reg)
3418 o1 = OPVCC(31, 339, 0, 0)
3419 }
3420
3421 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3422
3423 case 67:
3424 if p.From.Reg == REG_CR || p.To.Reg == REG_CR {
3425 c.ctxt.Diag("CR argument must be a conditional register field (CR0-CR7)\n%v", p)
3426 }
3427 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
3428
3429 case 68:
3430 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0)
3431 if p.From.Reg != REG_CR {
3432 v := uint32(1) << uint(7-(p.From.Reg&7))
3433 o1 |= 1<<20 | v<<12
3434 }
3435
3436 case 69:
3437 var v uint32
3438 if p.To.Reg == REG_CR {
3439 v = 0xff
3440 } else if p.To.Offset != 0 {
3441 v = uint32(p.To.Offset)
3442 } else {
3443 v = 1 << uint(7-(p.To.Reg&7))
3444 }
3445
3446 if bits.OnesCount32(v) == 1 {
3447 v |= 1 << 8
3448 }
3449
3450 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12
3451
3452 case 70:
3453 r := uint32(p.Reg&7) << 2
3454 if p.To.Type == obj.TYPE_CONST {
3455 o1 = AOP_IRR(c.opirr(p.As), r, uint32(p.From.Reg), uint32(uint16(p.To.Offset)))
3456 } else {
3457 o1 = AOP_RRR(c.oprrr(p.As), r, uint32(p.From.Reg), uint32(p.To.Reg))
3458 }
3459
3460 case 72:
3461 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
3462
3463 case 73:
3464 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
3465 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
3466 }
3467 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
3468
3469 case 77:
3470 if p.From.Type == obj.TYPE_CONST {
3471 if p.From.Offset > BIG || p.From.Offset < -BIG {
3472 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
3473 }
3474 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
3475 } else if p.From.Type == obj.TYPE_REG {
3476 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
3477 } else {
3478 c.ctxt.Diag("illegal syscall: %v", p)
3479 o1 = 0x7fe00008
3480 }
3481
3482 o2 = c.oprrr(p.As)
3483 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO)
3484
3485 case 78:
3486 o1 = 0
3488
3489
3490 case 74:
3491 var rel *obj.Reloc
3492 v := c.vregoff(&p.To)
3493
3494 inst := c.opstore(p.As)
3495
3496
3497 o1, o2, rel = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst, false)
3498
3499
3500 if o.ispfx {
3501 o1, o2 = pfxstore(p.As, p.From.Reg, REG_R0, PFX_R_PCREL)
3502 rel.Type = objabi.R_ADDRPOWER_PCREL34
3503 } else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3504 log.Fatalf("invalid offset for DS form load/store %v", p)
3505 }
3506
3507 case 75:
3508 var rel *obj.Reloc
3509 v := p.From.Offset
3510
3511
3512 inst := c.opload(p.As)
3513 switch p.From.Name {
3514 case obj.NAME_GOTREF, obj.NAME_TOCREF:
3515 if v != 0 {
3516 c.ctxt.Diag("invalid offset for GOT/TOC access %v", p)
3517 }
3518 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3519 o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3520 rel = obj.Addrel(c.cursym)
3521 rel.Off = int32(c.pc)
3522 rel.Siz = 8
3523 rel.Sym = p.From.Sym
3524 switch p.From.Name {
3525 case obj.NAME_GOTREF:
3526 rel.Type = objabi.R_ADDRPOWER_GOT
3527 case obj.NAME_TOCREF:
3528 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
3529 }
3530 default:
3531 reuseBaseReg := o.a6 == C_REG
3532
3533 o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
3534 }
3535
3536
3537 if o.ispfx {
3538 switch rel.Type {
3539 case objabi.R_ADDRPOWER, objabi.R_ADDRPOWER_DS,
3540 objabi.R_ADDRPOWER_TOCREL, objabi.R_ADDRPOWER_TOCREL_DS:
3541 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3542 rel.Type = objabi.R_ADDRPOWER_PCREL34
3543 case objabi.R_POWER_TLS_IE:
3544 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3545 rel.Type = objabi.R_POWER_TLS_IE_PCREL34
3546 case objabi.R_ADDRPOWER_GOT:
3547 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3548 rel.Type = objabi.R_ADDRPOWER_GOT_PCREL34
3549 default:
3550
3551 log.Fatalf("Unable convert TOC-relative relocation %v to PC-relative", rel.Type)
3552 }
3553 } else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3554 log.Fatalf("invalid offset for DS form load/store %v", p)
3555 }
3556
3557 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3558
3559 case 79:
3560 if p.From.Offset != 0 {
3561 c.ctxt.Diag("invalid offset against tls var %v", p)
3562 }
3563 rel := obj.Addrel(c.cursym)
3564 rel.Off = int32(c.pc)
3565 rel.Siz = 8
3566 rel.Sym = p.From.Sym
3567 if !o.ispfx {
3568 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R13, 0)
3569 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3570 rel.Type = objabi.R_POWER_TLS_LE
3571 } else {
3572 o1, o2 = pfxadd(p.To.Reg, REG_R13, PFX_R_ABS, 0)
3573 rel.Type = objabi.R_POWER_TLS_LE_TPREL34
3574 }
3575
3576 case 80:
3577 if p.From.Offset != 0 {
3578 c.ctxt.Diag("invalid offset against tls var %v", p)
3579 }
3580 rel := obj.Addrel(c.cursym)
3581 rel.Off = int32(c.pc)
3582 rel.Siz = 8
3583 rel.Sym = p.From.Sym
3584 rel.Type = objabi.R_POWER_TLS_IE
3585 if !o.ispfx {
3586 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3587 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
3588 } else {
3589 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3590 rel.Type = objabi.R_POWER_TLS_IE_PCREL34
3591 }
3592 o3 = AOP_RRR(OP_ADD, uint32(p.To.Reg), uint32(p.To.Reg), REG_R13)
3593 rel = obj.Addrel(c.cursym)
3594 rel.Off = int32(c.pc) + 8
3595 rel.Siz = 4
3596 rel.Sym = p.From.Sym
3597 rel.Type = objabi.R_POWER_TLS
3598
3599 case 82:
3600 if p.From.Type == obj.TYPE_REG {
3601
3602
3603
3604 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3605 } else if p.From3Type() == obj.TYPE_CONST {
3606
3607
3608 six := int(c.regoff(&p.From))
3609 st := int(c.regoff(p.GetFrom3()))
3610 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
3611 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
3612
3613
3614 uim := int(c.regoff(&p.From))
3615 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
3616 } else {
3617
3618
3619 sim := int(c.regoff(&p.From))
3620 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
3621 }
3622
3623 case 83:
3624 if p.From.Type == obj.TYPE_REG {
3625
3626
3627 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3628 } else if p.From.Type == obj.TYPE_CONST {
3629
3630
3631 shb := int(c.regoff(&p.From))
3632 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
3633 }
3634
3635 case 84:
3636 bc := c.vregoff(&p.From)
3637 if o.a1 == C_CRBIT {
3638
3639 bc = int64(p.From.Reg)
3640 }
3641
3642
3643 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
3644
3645 case 85:
3646
3647
3648 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
3649
3650 case 86:
3651
3652
3653 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3654
3655 case 87:
3656
3657
3658 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3659
3660 case 88:
3661 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3662
3663 case 89:
3664
3665
3666 uim := int(c.regoff(p.GetFrom3()))
3667 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
3668
3669 case 90:
3670 if p.From3Type() == obj.TYPE_NONE {
3671
3672
3673 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3674 } else if p.From3Type() == obj.TYPE_CONST {
3675
3676
3677 dm := int(c.regoff(p.GetFrom3()))
3678 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
3679 }
3680
3681 case 91:
3682
3683
3684 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3685
3686 case 92:
3687 if p.To.Type == obj.TYPE_CONST {
3688
3689 xf := int32(p.From.Reg)
3690 if REG_F0 <= xf && xf <= REG_F31 {
3691
3692 bf := int(c.regoff(&p.To)) << 2
3693 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3694 } else {
3695
3696 l := int(c.regoff(&p.To))
3697 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
3698 }
3699 } else if p.From3Type() == obj.TYPE_CONST {
3700
3701
3702 l := int(c.regoff(p.GetFrom3()))
3703 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
3704 } else if p.To.Type == obj.TYPE_REG {
3705 cr := int32(p.To.Reg)
3706 if REG_CR0 <= cr && cr <= REG_CR7 {
3707
3708
3709 bf := (int(p.To.Reg) & 7) << 2
3710 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3711 } else if p.From.Type == obj.TYPE_CONST {
3712
3713
3714 l := int(c.regoff(&p.From))
3715 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
3716 } else {
3717 switch p.As {
3718 case ACOPY, APASTECC:
3719 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
3720 default:
3721
3722
3723 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3724 }
3725 }
3726 }
3727
3728 case 93:
3729 if p.To.Type == obj.TYPE_CONST {
3730
3731
3732 bf := int(c.regoff(&p.To)) << 2
3733 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
3734 } else if p.Reg == 0 {
3735
3736
3737 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3738 }
3739
3740 case 94:
3741
3742
3743 cy := int(c.regoff(p.GetFrom3()))
3744 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
3745
3746 case 96:
3747
3748
3749 dq := int16(c.regoff(&p.From))
3750 if (dq & 15) != 0 {
3751 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3752 }
3753 o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq))
3754
3755 case 97:
3756
3757
3758 dq := int16(c.regoff(&p.To))
3759 if (dq & 15) != 0 {
3760 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3761 }
3762 o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq))
3763 case 98:
3764
3765 o1 = AOP_XX1(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3766 case 99:
3767
3768 o1 = AOP_XX1(c.opstore(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
3769 case 100:
3770 if p.From.Type == obj.TYPE_CONST {
3771
3772 uim := int(c.regoff(&p.From))
3773
3774
3775 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(uim))
3776 } else {
3777 c.ctxt.Diag("invalid ops for %v", p.As)
3778 }
3779 case 101:
3780 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg))
3781
3782 case 104:
3783 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3784
3785 case 106:
3786 v := int32(p.From.Reg)
3787 o1 = OPVCC(31, 339, 0, 0)
3788 o1 = AOP_RRR(o1, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3789 so := c.regoff(&p.To)
3790 o2 = AOP_IRR(c.opstore(AMOVD), uint32(REGTMP), uint32(p.To.Reg), uint32(so))
3791 if so&0x3 != 0 {
3792 log.Fatalf("invalid offset for DS form load/store %v", p)
3793 }
3794 if p.To.Reg == REGTMP {
3795 log.Fatalf("SPR move to memory will clobber R31 %v", p)
3796 }
3797
3798 case 107:
3799 v := int32(p.From.Reg)
3800 so := c.regoff(&p.From)
3801 o1 = AOP_IRR(c.opload(AMOVD), uint32(REGTMP), uint32(v), uint32(so))
3802 o2 = OPVCC(31, 467, 0, 0)
3803 v = int32(p.To.Reg)
3804 o2 = AOP_RRR(o2, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3805 if so&0x3 != 0 {
3806 log.Fatalf("invalid offset for DS form load/store %v", p)
3807 }
3808
3809 case 108:
3810 r := int(p.To.Reg)
3811 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
3812
3813 case 109:
3814 r := int(p.From.Reg)
3815
3816 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
3817
3818 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3819
3820 case 110:
3821 bfa := uint32(p.From.Reg) << 2
3822 rt := uint32(p.To.Reg)
3823 o1 = LOP_RRR(OP_SETB, bfa, rt, 0)
3824 }
3825
3826 out[0] = o1
3827 out[1] = o2
3828 out[2] = o3
3829 out[3] = o4
3830 out[4] = o5
3831 }
3832
3833 func (c *ctxt9) vregoff(a *obj.Addr) int64 {
3834 c.instoffset = 0
3835 if a != nil {
3836 c.aclass(a)
3837 }
3838 return c.instoffset
3839 }
3840
3841 func (c *ctxt9) regoff(a *obj.Addr) int32 {
3842 return int32(c.vregoff(a))
3843 }
3844
3845 func (c *ctxt9) oprrr(a obj.As) uint32 {
3846 switch a {
3847 case AADD:
3848 return OPVCC(31, 266, 0, 0)
3849 case AADDCC:
3850 return OPVCC(31, 266, 0, 1)
3851 case AADDV:
3852 return OPVCC(31, 266, 1, 0)
3853 case AADDVCC:
3854 return OPVCC(31, 266, 1, 1)
3855 case AADDC:
3856 return OPVCC(31, 10, 0, 0)
3857 case AADDCCC:
3858 return OPVCC(31, 10, 0, 1)
3859 case AADDCV:
3860 return OPVCC(31, 10, 1, 0)
3861 case AADDCVCC:
3862 return OPVCC(31, 10, 1, 1)
3863 case AADDE:
3864 return OPVCC(31, 138, 0, 0)
3865 case AADDECC:
3866 return OPVCC(31, 138, 0, 1)
3867 case AADDEV:
3868 return OPVCC(31, 138, 1, 0)
3869 case AADDEVCC:
3870 return OPVCC(31, 138, 1, 1)
3871 case AADDME:
3872 return OPVCC(31, 234, 0, 0)
3873 case AADDMECC:
3874 return OPVCC(31, 234, 0, 1)
3875 case AADDMEV:
3876 return OPVCC(31, 234, 1, 0)
3877 case AADDMEVCC:
3878 return OPVCC(31, 234, 1, 1)
3879 case AADDZE:
3880 return OPVCC(31, 202, 0, 0)
3881 case AADDZECC:
3882 return OPVCC(31, 202, 0, 1)
3883 case AADDZEV:
3884 return OPVCC(31, 202, 1, 0)
3885 case AADDZEVCC:
3886 return OPVCC(31, 202, 1, 1)
3887 case AADDEX:
3888 return OPVCC(31, 170, 0, 0)
3889
3890 case AAND:
3891 return OPVCC(31, 28, 0, 0)
3892 case AANDCC:
3893 return OPVCC(31, 28, 0, 1)
3894 case AANDN:
3895 return OPVCC(31, 60, 0, 0)
3896 case AANDNCC:
3897 return OPVCC(31, 60, 0, 1)
3898
3899 case ACMP:
3900 return OPVCC(31, 0, 0, 0) | 1<<21
3901 case ACMPU:
3902 return OPVCC(31, 32, 0, 0) | 1<<21
3903 case ACMPW:
3904 return OPVCC(31, 0, 0, 0)
3905 case ACMPWU:
3906 return OPVCC(31, 32, 0, 0)
3907 case ACMPB:
3908 return OPVCC(31, 508, 0, 0)
3909 case ACMPEQB:
3910 return OPVCC(31, 224, 0, 0)
3911
3912 case ACNTLZW:
3913 return OPVCC(31, 26, 0, 0)
3914 case ACNTLZWCC:
3915 return OPVCC(31, 26, 0, 1)
3916 case ACNTLZD:
3917 return OPVCC(31, 58, 0, 0)
3918 case ACNTLZDCC:
3919 return OPVCC(31, 58, 0, 1)
3920
3921 case ACRAND:
3922 return OPVCC(19, 257, 0, 0)
3923 case ACRANDN:
3924 return OPVCC(19, 129, 0, 0)
3925 case ACREQV:
3926 return OPVCC(19, 289, 0, 0)
3927 case ACRNAND:
3928 return OPVCC(19, 225, 0, 0)
3929 case ACRNOR:
3930 return OPVCC(19, 33, 0, 0)
3931 case ACROR:
3932 return OPVCC(19, 449, 0, 0)
3933 case ACRORN:
3934 return OPVCC(19, 417, 0, 0)
3935 case ACRXOR:
3936 return OPVCC(19, 193, 0, 0)
3937
3938 case ADCBF:
3939 return OPVCC(31, 86, 0, 0)
3940 case ADCBI:
3941 return OPVCC(31, 470, 0, 0)
3942 case ADCBST:
3943 return OPVCC(31, 54, 0, 0)
3944 case ADCBT:
3945 return OPVCC(31, 278, 0, 0)
3946 case ADCBTST:
3947 return OPVCC(31, 246, 0, 0)
3948 case ADCBZ:
3949 return OPVCC(31, 1014, 0, 0)
3950
3951 case AMODUD:
3952 return OPVCC(31, 265, 0, 0)
3953 case AMODUW:
3954 return OPVCC(31, 267, 0, 0)
3955 case AMODSD:
3956 return OPVCC(31, 777, 0, 0)
3957 case AMODSW:
3958 return OPVCC(31, 779, 0, 0)
3959
3960 case ADIVW, AREM:
3961 return OPVCC(31, 491, 0, 0)
3962
3963 case ADIVWCC:
3964 return OPVCC(31, 491, 0, 1)
3965
3966 case ADIVWV:
3967 return OPVCC(31, 491, 1, 0)
3968
3969 case ADIVWVCC:
3970 return OPVCC(31, 491, 1, 1)
3971
3972 case ADIVWU, AREMU:
3973 return OPVCC(31, 459, 0, 0)
3974
3975 case ADIVWUCC:
3976 return OPVCC(31, 459, 0, 1)
3977
3978 case ADIVWUV:
3979 return OPVCC(31, 459, 1, 0)
3980
3981 case ADIVWUVCC:
3982 return OPVCC(31, 459, 1, 1)
3983
3984 case ADIVD, AREMD:
3985 return OPVCC(31, 489, 0, 0)
3986
3987 case ADIVDCC:
3988 return OPVCC(31, 489, 0, 1)
3989
3990 case ADIVDE:
3991 return OPVCC(31, 425, 0, 0)
3992
3993 case ADIVDECC:
3994 return OPVCC(31, 425, 0, 1)
3995
3996 case ADIVDEU:
3997 return OPVCC(31, 393, 0, 0)
3998
3999 case ADIVDEUCC:
4000 return OPVCC(31, 393, 0, 1)
4001
4002 case ADIVDV:
4003 return OPVCC(31, 489, 1, 0)
4004
4005 case ADIVDVCC:
4006 return OPVCC(31, 489, 1, 1)
4007
4008 case ADIVDU, AREMDU:
4009 return OPVCC(31, 457, 0, 0)
4010
4011 case ADIVDUCC:
4012 return OPVCC(31, 457, 0, 1)
4013
4014 case ADIVDUV:
4015 return OPVCC(31, 457, 1, 0)
4016
4017 case ADIVDUVCC:
4018 return OPVCC(31, 457, 1, 1)
4019
4020 case AEIEIO:
4021 return OPVCC(31, 854, 0, 0)
4022
4023 case AEQV:
4024 return OPVCC(31, 284, 0, 0)
4025 case AEQVCC:
4026 return OPVCC(31, 284, 0, 1)
4027
4028 case AEXTSB:
4029 return OPVCC(31, 954, 0, 0)
4030 case AEXTSBCC:
4031 return OPVCC(31, 954, 0, 1)
4032 case AEXTSH:
4033 return OPVCC(31, 922, 0, 0)
4034 case AEXTSHCC:
4035 return OPVCC(31, 922, 0, 1)
4036 case AEXTSW:
4037 return OPVCC(31, 986, 0, 0)
4038 case AEXTSWCC:
4039 return OPVCC(31, 986, 0, 1)
4040
4041 case AFABS:
4042 return OPVCC(63, 264, 0, 0)
4043 case AFABSCC:
4044 return OPVCC(63, 264, 0, 1)
4045 case AFADD:
4046 return OPVCC(63, 21, 0, 0)
4047 case AFADDCC:
4048 return OPVCC(63, 21, 0, 1)
4049 case AFADDS:
4050 return OPVCC(59, 21, 0, 0)
4051 case AFADDSCC:
4052 return OPVCC(59, 21, 0, 1)
4053 case AFCMPO:
4054 return OPVCC(63, 32, 0, 0)
4055 case AFCMPU:
4056 return OPVCC(63, 0, 0, 0)
4057 case AFCFID:
4058 return OPVCC(63, 846, 0, 0)
4059 case AFCFIDCC:
4060 return OPVCC(63, 846, 0, 1)
4061 case AFCFIDU:
4062 return OPVCC(63, 974, 0, 0)
4063 case AFCFIDUCC:
4064 return OPVCC(63, 974, 0, 1)
4065 case AFCFIDS:
4066 return OPVCC(59, 846, 0, 0)
4067 case AFCFIDSCC:
4068 return OPVCC(59, 846, 0, 1)
4069 case AFCTIW:
4070 return OPVCC(63, 14, 0, 0)
4071 case AFCTIWCC:
4072 return OPVCC(63, 14, 0, 1)
4073 case AFCTIWZ:
4074 return OPVCC(63, 15, 0, 0)
4075 case AFCTIWZCC:
4076 return OPVCC(63, 15, 0, 1)
4077 case AFCTID:
4078 return OPVCC(63, 814, 0, 0)
4079 case AFCTIDCC:
4080 return OPVCC(63, 814, 0, 1)
4081 case AFCTIDZ:
4082 return OPVCC(63, 815, 0, 0)
4083 case AFCTIDZCC:
4084 return OPVCC(63, 815, 0, 1)
4085 case AFDIV:
4086 return OPVCC(63, 18, 0, 0)
4087 case AFDIVCC:
4088 return OPVCC(63, 18, 0, 1)
4089 case AFDIVS:
4090 return OPVCC(59, 18, 0, 0)
4091 case AFDIVSCC:
4092 return OPVCC(59, 18, 0, 1)
4093 case AFMADD:
4094 return OPVCC(63, 29, 0, 0)
4095 case AFMADDCC:
4096 return OPVCC(63, 29, 0, 1)
4097 case AFMADDS:
4098 return OPVCC(59, 29, 0, 0)
4099 case AFMADDSCC:
4100 return OPVCC(59, 29, 0, 1)
4101
4102 case AFMOVS, AFMOVD:
4103 return OPVCC(63, 72, 0, 0)
4104 case AFMOVDCC:
4105 return OPVCC(63, 72, 0, 1)
4106 case AFMSUB:
4107 return OPVCC(63, 28, 0, 0)
4108 case AFMSUBCC:
4109 return OPVCC(63, 28, 0, 1)
4110 case AFMSUBS:
4111 return OPVCC(59, 28, 0, 0)
4112 case AFMSUBSCC:
4113 return OPVCC(59, 28, 0, 1)
4114 case AFMUL:
4115 return OPVCC(63, 25, 0, 0)
4116 case AFMULCC:
4117 return OPVCC(63, 25, 0, 1)
4118 case AFMULS:
4119 return OPVCC(59, 25, 0, 0)
4120 case AFMULSCC:
4121 return OPVCC(59, 25, 0, 1)
4122 case AFNABS:
4123 return OPVCC(63, 136, 0, 0)
4124 case AFNABSCC:
4125 return OPVCC(63, 136, 0, 1)
4126 case AFNEG:
4127 return OPVCC(63, 40, 0, 0)
4128 case AFNEGCC:
4129 return OPVCC(63, 40, 0, 1)
4130 case AFNMADD:
4131 return OPVCC(63, 31, 0, 0)
4132 case AFNMADDCC:
4133 return OPVCC(63, 31, 0, 1)
4134 case AFNMADDS:
4135 return OPVCC(59, 31, 0, 0)
4136 case AFNMADDSCC:
4137 return OPVCC(59, 31, 0, 1)
4138 case AFNMSUB:
4139 return OPVCC(63, 30, 0, 0)
4140 case AFNMSUBCC:
4141 return OPVCC(63, 30, 0, 1)
4142 case AFNMSUBS:
4143 return OPVCC(59, 30, 0, 0)
4144 case AFNMSUBSCC:
4145 return OPVCC(59, 30, 0, 1)
4146 case AFCPSGN:
4147 return OPVCC(63, 8, 0, 0)
4148 case AFCPSGNCC:
4149 return OPVCC(63, 8, 0, 1)
4150 case AFRES:
4151 return OPVCC(59, 24, 0, 0)
4152 case AFRESCC:
4153 return OPVCC(59, 24, 0, 1)
4154 case AFRIM:
4155 return OPVCC(63, 488, 0, 0)
4156 case AFRIMCC:
4157 return OPVCC(63, 488, 0, 1)
4158 case AFRIP:
4159 return OPVCC(63, 456, 0, 0)
4160 case AFRIPCC:
4161 return OPVCC(63, 456, 0, 1)
4162 case AFRIZ:
4163 return OPVCC(63, 424, 0, 0)
4164 case AFRIZCC:
4165 return OPVCC(63, 424, 0, 1)
4166 case AFRIN:
4167 return OPVCC(63, 392, 0, 0)
4168 case AFRINCC:
4169 return OPVCC(63, 392, 0, 1)
4170 case AFRSP:
4171 return OPVCC(63, 12, 0, 0)
4172 case AFRSPCC:
4173 return OPVCC(63, 12, 0, 1)
4174 case AFRSQRTE:
4175 return OPVCC(63, 26, 0, 0)
4176 case AFRSQRTECC:
4177 return OPVCC(63, 26, 0, 1)
4178 case AFSEL:
4179 return OPVCC(63, 23, 0, 0)
4180 case AFSELCC:
4181 return OPVCC(63, 23, 0, 1)
4182 case AFSQRT:
4183 return OPVCC(63, 22, 0, 0)
4184 case AFSQRTCC:
4185 return OPVCC(63, 22, 0, 1)
4186 case AFSQRTS:
4187 return OPVCC(59, 22, 0, 0)
4188 case AFSQRTSCC:
4189 return OPVCC(59, 22, 0, 1)
4190 case AFSUB:
4191 return OPVCC(63, 20, 0, 0)
4192 case AFSUBCC:
4193 return OPVCC(63, 20, 0, 1)
4194 case AFSUBS:
4195 return OPVCC(59, 20, 0, 0)
4196 case AFSUBSCC:
4197 return OPVCC(59, 20, 0, 1)
4198
4199 case AICBI:
4200 return OPVCC(31, 982, 0, 0)
4201 case AISYNC:
4202 return OPVCC(19, 150, 0, 0)
4203
4204 case AMTFSB0:
4205 return OPVCC(63, 70, 0, 0)
4206 case AMTFSB0CC:
4207 return OPVCC(63, 70, 0, 1)
4208 case AMTFSB1:
4209 return OPVCC(63, 38, 0, 0)
4210 case AMTFSB1CC:
4211 return OPVCC(63, 38, 0, 1)
4212
4213 case AMULHW:
4214 return OPVCC(31, 75, 0, 0)
4215 case AMULHWCC:
4216 return OPVCC(31, 75, 0, 1)
4217 case AMULHWU:
4218 return OPVCC(31, 11, 0, 0)
4219 case AMULHWUCC:
4220 return OPVCC(31, 11, 0, 1)
4221 case AMULLW:
4222 return OPVCC(31, 235, 0, 0)
4223 case AMULLWCC:
4224 return OPVCC(31, 235, 0, 1)
4225 case AMULLWV:
4226 return OPVCC(31, 235, 1, 0)
4227 case AMULLWVCC:
4228 return OPVCC(31, 235, 1, 1)
4229
4230 case AMULHD:
4231 return OPVCC(31, 73, 0, 0)
4232 case AMULHDCC:
4233 return OPVCC(31, 73, 0, 1)
4234 case AMULHDU:
4235 return OPVCC(31, 9, 0, 0)
4236 case AMULHDUCC:
4237 return OPVCC(31, 9, 0, 1)
4238 case AMULLD:
4239 return OPVCC(31, 233, 0, 0)
4240 case AMULLDCC:
4241 return OPVCC(31, 233, 0, 1)
4242 case AMULLDV:
4243 return OPVCC(31, 233, 1, 0)
4244 case AMULLDVCC:
4245 return OPVCC(31, 233, 1, 1)
4246
4247 case ANAND:
4248 return OPVCC(31, 476, 0, 0)
4249 case ANANDCC:
4250 return OPVCC(31, 476, 0, 1)
4251 case ANEG:
4252 return OPVCC(31, 104, 0, 0)
4253 case ANEGCC:
4254 return OPVCC(31, 104, 0, 1)
4255 case ANEGV:
4256 return OPVCC(31, 104, 1, 0)
4257 case ANEGVCC:
4258 return OPVCC(31, 104, 1, 1)
4259 case ANOR:
4260 return OPVCC(31, 124, 0, 0)
4261 case ANORCC:
4262 return OPVCC(31, 124, 0, 1)
4263 case AOR:
4264 return OPVCC(31, 444, 0, 0)
4265 case AORCC:
4266 return OPVCC(31, 444, 0, 1)
4267 case AORN:
4268 return OPVCC(31, 412, 0, 0)
4269 case AORNCC:
4270 return OPVCC(31, 412, 0, 1)
4271
4272 case APOPCNTD:
4273 return OPVCC(31, 506, 0, 0)
4274 case APOPCNTW:
4275 return OPVCC(31, 378, 0, 0)
4276 case APOPCNTB:
4277 return OPVCC(31, 122, 0, 0)
4278 case ACNTTZW:
4279 return OPVCC(31, 538, 0, 0)
4280 case ACNTTZWCC:
4281 return OPVCC(31, 538, 0, 1)
4282 case ACNTTZD:
4283 return OPVCC(31, 570, 0, 0)
4284 case ACNTTZDCC:
4285 return OPVCC(31, 570, 0, 1)
4286
4287 case ARFI:
4288 return OPVCC(19, 50, 0, 0)
4289 case ARFCI:
4290 return OPVCC(19, 51, 0, 0)
4291 case ARFID:
4292 return OPVCC(19, 18, 0, 0)
4293 case AHRFID:
4294 return OPVCC(19, 274, 0, 0)
4295
4296 case ARLWNM:
4297 return OPVCC(23, 0, 0, 0)
4298 case ARLWNMCC:
4299 return OPVCC(23, 0, 0, 1)
4300
4301 case ARLDCL:
4302 return OPVCC(30, 8, 0, 0)
4303 case ARLDCLCC:
4304 return OPVCC(30, 0, 0, 1)
4305
4306 case ARLDCR:
4307 return OPVCC(30, 9, 0, 0)
4308 case ARLDCRCC:
4309 return OPVCC(30, 9, 0, 1)
4310
4311 case ARLDICL:
4312 return OPVCC(30, 0, 0, 0)
4313 case ARLDICLCC:
4314 return OPVCC(30, 0, 0, 1)
4315 case ARLDICR:
4316 return OPMD(30, 1, 0)
4317 case ARLDICRCC:
4318 return OPMD(30, 1, 1)
4319
4320 case ARLDIC:
4321 return OPMD(30, 2, 0)
4322 case ARLDICCC:
4323 return OPMD(30, 2, 1)
4324
4325 case ASYSCALL:
4326 return OPVCC(17, 1, 0, 0)
4327
4328 case ASLW:
4329 return OPVCC(31, 24, 0, 0)
4330 case ASLWCC:
4331 return OPVCC(31, 24, 0, 1)
4332 case ASLD:
4333 return OPVCC(31, 27, 0, 0)
4334 case ASLDCC:
4335 return OPVCC(31, 27, 0, 1)
4336
4337 case ASRAW:
4338 return OPVCC(31, 792, 0, 0)
4339 case ASRAWCC:
4340 return OPVCC(31, 792, 0, 1)
4341 case ASRAD:
4342 return OPVCC(31, 794, 0, 0)
4343 case ASRADCC:
4344 return OPVCC(31, 794, 0, 1)
4345
4346 case AEXTSWSLI:
4347 return OPVCC(31, 445, 0, 0)
4348 case AEXTSWSLICC:
4349 return OPVCC(31, 445, 0, 1)
4350
4351 case ASRW:
4352 return OPVCC(31, 536, 0, 0)
4353 case ASRWCC:
4354 return OPVCC(31, 536, 0, 1)
4355 case ASRD:
4356 return OPVCC(31, 539, 0, 0)
4357 case ASRDCC:
4358 return OPVCC(31, 539, 0, 1)
4359
4360 case ASUB:
4361 return OPVCC(31, 40, 0, 0)
4362 case ASUBCC:
4363 return OPVCC(31, 40, 0, 1)
4364 case ASUBV:
4365 return OPVCC(31, 40, 1, 0)
4366 case ASUBVCC:
4367 return OPVCC(31, 40, 1, 1)
4368 case ASUBC:
4369 return OPVCC(31, 8, 0, 0)
4370 case ASUBCCC:
4371 return OPVCC(31, 8, 0, 1)
4372 case ASUBCV:
4373 return OPVCC(31, 8, 1, 0)
4374 case ASUBCVCC:
4375 return OPVCC(31, 8, 1, 1)
4376 case ASUBE:
4377 return OPVCC(31, 136, 0, 0)
4378 case ASUBECC:
4379 return OPVCC(31, 136, 0, 1)
4380 case ASUBEV:
4381 return OPVCC(31, 136, 1, 0)
4382 case ASUBEVCC:
4383 return OPVCC(31, 136, 1, 1)
4384 case ASUBME:
4385 return OPVCC(31, 232, 0, 0)
4386 case ASUBMECC:
4387 return OPVCC(31, 232, 0, 1)
4388 case ASUBMEV:
4389 return OPVCC(31, 232, 1, 0)
4390 case ASUBMEVCC:
4391 return OPVCC(31, 232, 1, 1)
4392 case ASUBZE:
4393 return OPVCC(31, 200, 0, 0)
4394 case ASUBZECC:
4395 return OPVCC(31, 200, 0, 1)
4396 case ASUBZEV:
4397 return OPVCC(31, 200, 1, 0)
4398 case ASUBZEVCC:
4399 return OPVCC(31, 200, 1, 1)
4400
4401 case ASYNC:
4402 return OPVCC(31, 598, 0, 0)
4403 case ALWSYNC:
4404 return OPVCC(31, 598, 0, 0) | 1<<21
4405
4406 case APTESYNC:
4407 return OPVCC(31, 598, 0, 0) | 2<<21
4408
4409 case ATLBIE:
4410 return OPVCC(31, 306, 0, 0)
4411 case ATLBIEL:
4412 return OPVCC(31, 274, 0, 0)
4413 case ATLBSYNC:
4414 return OPVCC(31, 566, 0, 0)
4415 case ASLBIA:
4416 return OPVCC(31, 498, 0, 0)
4417 case ASLBIE:
4418 return OPVCC(31, 434, 0, 0)
4419 case ASLBMFEE:
4420 return OPVCC(31, 915, 0, 0)
4421 case ASLBMFEV:
4422 return OPVCC(31, 851, 0, 0)
4423 case ASLBMTE:
4424 return OPVCC(31, 402, 0, 0)
4425
4426 case ATW:
4427 return OPVCC(31, 4, 0, 0)
4428 case ATD:
4429 return OPVCC(31, 68, 0, 0)
4430
4431
4432
4433
4434 case AVAND:
4435 return OPVX(4, 1028, 0, 0)
4436 case AVANDC:
4437 return OPVX(4, 1092, 0, 0)
4438 case AVNAND:
4439 return OPVX(4, 1412, 0, 0)
4440
4441 case AVOR:
4442 return OPVX(4, 1156, 0, 0)
4443 case AVORC:
4444 return OPVX(4, 1348, 0, 0)
4445 case AVNOR:
4446 return OPVX(4, 1284, 0, 0)
4447 case AVXOR:
4448 return OPVX(4, 1220, 0, 0)
4449 case AVEQV:
4450 return OPVX(4, 1668, 0, 0)
4451
4452 case AVADDUBM:
4453 return OPVX(4, 0, 0, 0)
4454 case AVADDUHM:
4455 return OPVX(4, 64, 0, 0)
4456 case AVADDUWM:
4457 return OPVX(4, 128, 0, 0)
4458 case AVADDUDM:
4459 return OPVX(4, 192, 0, 0)
4460 case AVADDUQM:
4461 return OPVX(4, 256, 0, 0)
4462
4463 case AVADDCUQ:
4464 return OPVX(4, 320, 0, 0)
4465 case AVADDCUW:
4466 return OPVX(4, 384, 0, 0)
4467
4468 case AVADDUBS:
4469 return OPVX(4, 512, 0, 0)
4470 case AVADDUHS:
4471 return OPVX(4, 576, 0, 0)
4472 case AVADDUWS:
4473 return OPVX(4, 640, 0, 0)
4474
4475 case AVADDSBS:
4476 return OPVX(4, 768, 0, 0)
4477 case AVADDSHS:
4478 return OPVX(4, 832, 0, 0)
4479 case AVADDSWS:
4480 return OPVX(4, 896, 0, 0)
4481
4482 case AVADDEUQM:
4483 return OPVX(4, 60, 0, 0)
4484 case AVADDECUQ:
4485 return OPVX(4, 61, 0, 0)
4486
4487 case AVMULESB:
4488 return OPVX(4, 776, 0, 0)
4489 case AVMULOSB:
4490 return OPVX(4, 264, 0, 0)
4491 case AVMULEUB:
4492 return OPVX(4, 520, 0, 0)
4493 case AVMULOUB:
4494 return OPVX(4, 8, 0, 0)
4495 case AVMULESH:
4496 return OPVX(4, 840, 0, 0)
4497 case AVMULOSH:
4498 return OPVX(4, 328, 0, 0)
4499 case AVMULEUH:
4500 return OPVX(4, 584, 0, 0)
4501 case AVMULOUH:
4502 return OPVX(4, 72, 0, 0)
4503 case AVMULESW:
4504 return OPVX(4, 904, 0, 0)
4505 case AVMULOSW:
4506 return OPVX(4, 392, 0, 0)
4507 case AVMULEUW:
4508 return OPVX(4, 648, 0, 0)
4509 case AVMULOUW:
4510 return OPVX(4, 136, 0, 0)
4511 case AVMULUWM:
4512 return OPVX(4, 137, 0, 0)
4513
4514 case AVPMSUMB:
4515 return OPVX(4, 1032, 0, 0)
4516 case AVPMSUMH:
4517 return OPVX(4, 1096, 0, 0)
4518 case AVPMSUMW:
4519 return OPVX(4, 1160, 0, 0)
4520 case AVPMSUMD:
4521 return OPVX(4, 1224, 0, 0)
4522
4523 case AVMSUMUDM:
4524 return OPVX(4, 35, 0, 0)
4525
4526 case AVSUBUBM:
4527 return OPVX(4, 1024, 0, 0)
4528 case AVSUBUHM:
4529 return OPVX(4, 1088, 0, 0)
4530 case AVSUBUWM:
4531 return OPVX(4, 1152, 0, 0)
4532 case AVSUBUDM:
4533 return OPVX(4, 1216, 0, 0)
4534 case AVSUBUQM:
4535 return OPVX(4, 1280, 0, 0)
4536
4537 case AVSUBCUQ:
4538 return OPVX(4, 1344, 0, 0)
4539 case AVSUBCUW:
4540 return OPVX(4, 1408, 0, 0)
4541
4542 case AVSUBUBS:
4543 return OPVX(4, 1536, 0, 0)
4544 case AVSUBUHS:
4545 return OPVX(4, 1600, 0, 0)
4546 case AVSUBUWS:
4547 return OPVX(4, 1664, 0, 0)
4548
4549 case AVSUBSBS:
4550 return OPVX(4, 1792, 0, 0)
4551 case AVSUBSHS:
4552 return OPVX(4, 1856, 0, 0)
4553 case AVSUBSWS:
4554 return OPVX(4, 1920, 0, 0)
4555
4556 case AVSUBEUQM:
4557 return OPVX(4, 62, 0, 0)
4558 case AVSUBECUQ:
4559 return OPVX(4, 63, 0, 0)
4560
4561 case AVRLB:
4562 return OPVX(4, 4, 0, 0)
4563 case AVRLH:
4564 return OPVX(4, 68, 0, 0)
4565 case AVRLW:
4566 return OPVX(4, 132, 0, 0)
4567 case AVRLD:
4568 return OPVX(4, 196, 0, 0)
4569
4570 case AVMRGOW:
4571 return OPVX(4, 1676, 0, 0)
4572 case AVMRGEW:
4573 return OPVX(4, 1932, 0, 0)
4574
4575 case AVSLB:
4576 return OPVX(4, 260, 0, 0)
4577 case AVSLH:
4578 return OPVX(4, 324, 0, 0)
4579 case AVSLW:
4580 return OPVX(4, 388, 0, 0)
4581 case AVSL:
4582 return OPVX(4, 452, 0, 0)
4583 case AVSLO:
4584 return OPVX(4, 1036, 0, 0)
4585 case AVSRB:
4586 return OPVX(4, 516, 0, 0)
4587 case AVSRH:
4588 return OPVX(4, 580, 0, 0)
4589 case AVSRW:
4590 return OPVX(4, 644, 0, 0)
4591 case AVSR:
4592 return OPVX(4, 708, 0, 0)
4593 case AVSRO:
4594 return OPVX(4, 1100, 0, 0)
4595 case AVSLD:
4596 return OPVX(4, 1476, 0, 0)
4597 case AVSRD:
4598 return OPVX(4, 1732, 0, 0)
4599
4600 case AVSRAB:
4601 return OPVX(4, 772, 0, 0)
4602 case AVSRAH:
4603 return OPVX(4, 836, 0, 0)
4604 case AVSRAW:
4605 return OPVX(4, 900, 0, 0)
4606 case AVSRAD:
4607 return OPVX(4, 964, 0, 0)
4608
4609 case AVBPERMQ:
4610 return OPVC(4, 1356, 0, 0)
4611 case AVBPERMD:
4612 return OPVC(4, 1484, 0, 0)
4613
4614 case AVCLZB:
4615 return OPVX(4, 1794, 0, 0)
4616 case AVCLZH:
4617 return OPVX(4, 1858, 0, 0)
4618 case AVCLZW:
4619 return OPVX(4, 1922, 0, 0)
4620 case AVCLZD:
4621 return OPVX(4, 1986, 0, 0)
4622
4623 case AVCLZLSBB:
4624 return OPVX(4, 1538, 0, 0)
4625 case AVCTZLSBB:
4626 return OPVX(4, 1538, 0, 0) | 1<<16
4627
4628 case AVPOPCNTB:
4629 return OPVX(4, 1795, 0, 0)
4630 case AVPOPCNTH:
4631 return OPVX(4, 1859, 0, 0)
4632 case AVPOPCNTW:
4633 return OPVX(4, 1923, 0, 0)
4634 case AVPOPCNTD:
4635 return OPVX(4, 1987, 0, 0)
4636
4637 case AVCMPEQUB:
4638 return OPVC(4, 6, 0, 0)
4639 case AVCMPEQUBCC:
4640 return OPVC(4, 6, 0, 1)
4641 case AVCMPEQUH:
4642 return OPVC(4, 70, 0, 0)
4643 case AVCMPEQUHCC:
4644 return OPVC(4, 70, 0, 1)
4645 case AVCMPEQUW:
4646 return OPVC(4, 134, 0, 0)
4647 case AVCMPEQUWCC:
4648 return OPVC(4, 134, 0, 1)
4649 case AVCMPEQUD:
4650 return OPVC(4, 199, 0, 0)
4651 case AVCMPEQUDCC:
4652 return OPVC(4, 199, 0, 1)
4653
4654 case AVCMPGTUB:
4655 return OPVC(4, 518, 0, 0)
4656 case AVCMPGTUBCC:
4657 return OPVC(4, 518, 0, 1)
4658 case AVCMPGTUH:
4659 return OPVC(4, 582, 0, 0)
4660 case AVCMPGTUHCC:
4661 return OPVC(4, 582, 0, 1)
4662 case AVCMPGTUW:
4663 return OPVC(4, 646, 0, 0)
4664 case AVCMPGTUWCC:
4665 return OPVC(4, 646, 0, 1)
4666 case AVCMPGTUD:
4667 return OPVC(4, 711, 0, 0)
4668 case AVCMPGTUDCC:
4669 return OPVC(4, 711, 0, 1)
4670 case AVCMPGTSB:
4671 return OPVC(4, 774, 0, 0)
4672 case AVCMPGTSBCC:
4673 return OPVC(4, 774, 0, 1)
4674 case AVCMPGTSH:
4675 return OPVC(4, 838, 0, 0)
4676 case AVCMPGTSHCC:
4677 return OPVC(4, 838, 0, 1)
4678 case AVCMPGTSW:
4679 return OPVC(4, 902, 0, 0)
4680 case AVCMPGTSWCC:
4681 return OPVC(4, 902, 0, 1)
4682 case AVCMPGTSD:
4683 return OPVC(4, 967, 0, 0)
4684 case AVCMPGTSDCC:
4685 return OPVC(4, 967, 0, 1)
4686
4687 case AVCMPNEZB:
4688 return OPVC(4, 263, 0, 0)
4689 case AVCMPNEZBCC:
4690 return OPVC(4, 263, 0, 1)
4691 case AVCMPNEB:
4692 return OPVC(4, 7, 0, 0)
4693 case AVCMPNEBCC:
4694 return OPVC(4, 7, 0, 1)
4695 case AVCMPNEH:
4696 return OPVC(4, 71, 0, 0)
4697 case AVCMPNEHCC:
4698 return OPVC(4, 71, 0, 1)
4699 case AVCMPNEW:
4700 return OPVC(4, 135, 0, 0)
4701 case AVCMPNEWCC:
4702 return OPVC(4, 135, 0, 1)
4703
4704 case AVPERM:
4705 return OPVX(4, 43, 0, 0)
4706 case AVPERMXOR:
4707 return OPVX(4, 45, 0, 0)
4708 case AVPERMR:
4709 return OPVX(4, 59, 0, 0)
4710
4711 case AVSEL:
4712 return OPVX(4, 42, 0, 0)
4713
4714 case AVCIPHER:
4715 return OPVX(4, 1288, 0, 0)
4716 case AVCIPHERLAST:
4717 return OPVX(4, 1289, 0, 0)
4718 case AVNCIPHER:
4719 return OPVX(4, 1352, 0, 0)
4720 case AVNCIPHERLAST:
4721 return OPVX(4, 1353, 0, 0)
4722 case AVSBOX:
4723 return OPVX(4, 1480, 0, 0)
4724
4725
4726
4727
4728 case AMFVSRD, AMFVRD, AMFFPRD:
4729 return OPVXX1(31, 51, 0)
4730 case AMFVSRWZ:
4731 return OPVXX1(31, 115, 0)
4732 case AMFVSRLD:
4733 return OPVXX1(31, 307, 0)
4734
4735 case AMTVSRD, AMTFPRD, AMTVRD:
4736 return OPVXX1(31, 179, 0)
4737 case AMTVSRWA:
4738 return OPVXX1(31, 211, 0)
4739 case AMTVSRWZ:
4740 return OPVXX1(31, 243, 0)
4741 case AMTVSRDD:
4742 return OPVXX1(31, 435, 0)
4743 case AMTVSRWS:
4744 return OPVXX1(31, 403, 0)
4745
4746 case AXXLAND:
4747 return OPVXX3(60, 130, 0)
4748 case AXXLANDC:
4749 return OPVXX3(60, 138, 0)
4750 case AXXLEQV:
4751 return OPVXX3(60, 186, 0)
4752 case AXXLNAND:
4753 return OPVXX3(60, 178, 0)
4754
4755 case AXXLORC:
4756 return OPVXX3(60, 170, 0)
4757 case AXXLNOR:
4758 return OPVXX3(60, 162, 0)
4759 case AXXLOR, AXXLORQ:
4760 return OPVXX3(60, 146, 0)
4761 case AXXLXOR:
4762 return OPVXX3(60, 154, 0)
4763 case AXSMINJDP:
4764 return OPVXX3(60, 152, 0)
4765 case AXSMAXJDP:
4766 return OPVXX3(60, 144, 0)
4767
4768 case AXXSEL:
4769 return OPVXX4(60, 3, 0)
4770
4771 case AXXMRGHW:
4772 return OPVXX3(60, 18, 0)
4773 case AXXMRGLW:
4774 return OPVXX3(60, 50, 0)
4775
4776 case AXXSPLTW:
4777 return OPVXX2(60, 164, 0)
4778
4779 case AXXSPLTIB:
4780 return OPVCC(60, 360, 0, 0)
4781
4782 case AXXPERM:
4783 return OPVXX3(60, 26, 0)
4784 case AXXPERMDI:
4785 return OPVXX3(60, 10, 0)
4786
4787 case AXXSLDWI:
4788 return OPVXX3(60, 2, 0)
4789
4790 case AXXBRQ:
4791 return OPVXX2VA(60, 475, 31)
4792 case AXXBRD:
4793 return OPVXX2VA(60, 475, 23)
4794 case AXXBRW:
4795 return OPVXX2VA(60, 475, 15)
4796 case AXXBRH:
4797 return OPVXX2VA(60, 475, 7)
4798
4799 case AXSCVDPSP:
4800 return OPVXX2(60, 265, 0)
4801 case AXSCVSPDP:
4802 return OPVXX2(60, 329, 0)
4803 case AXSCVDPSPN:
4804 return OPVXX2(60, 267, 0)
4805 case AXSCVSPDPN:
4806 return OPVXX2(60, 331, 0)
4807
4808 case AXVCVDPSP:
4809 return OPVXX2(60, 393, 0)
4810 case AXVCVSPDP:
4811 return OPVXX2(60, 457, 0)
4812
4813 case AXSCVDPSXDS:
4814 return OPVXX2(60, 344, 0)
4815 case AXSCVDPSXWS:
4816 return OPVXX2(60, 88, 0)
4817 case AXSCVDPUXDS:
4818 return OPVXX2(60, 328, 0)
4819 case AXSCVDPUXWS:
4820 return OPVXX2(60, 72, 0)
4821
4822 case AXSCVSXDDP:
4823 return OPVXX2(60, 376, 0)
4824 case AXSCVUXDDP:
4825 return OPVXX2(60, 360, 0)
4826 case AXSCVSXDSP:
4827 return OPVXX2(60, 312, 0)
4828 case AXSCVUXDSP:
4829 return OPVXX2(60, 296, 0)
4830
4831 case AXVCVDPSXDS:
4832 return OPVXX2(60, 472, 0)
4833 case AXVCVDPSXWS:
4834 return OPVXX2(60, 216, 0)
4835 case AXVCVDPUXDS:
4836 return OPVXX2(60, 456, 0)
4837 case AXVCVDPUXWS:
4838 return OPVXX2(60, 200, 0)
4839 case AXVCVSPSXDS:
4840 return OPVXX2(60, 408, 0)
4841 case AXVCVSPSXWS:
4842 return OPVXX2(60, 152, 0)
4843 case AXVCVSPUXDS:
4844 return OPVXX2(60, 392, 0)
4845 case AXVCVSPUXWS:
4846 return OPVXX2(60, 136, 0)
4847
4848 case AXVCVSXDDP:
4849 return OPVXX2(60, 504, 0)
4850 case AXVCVSXWDP:
4851 return OPVXX2(60, 248, 0)
4852 case AXVCVUXDDP:
4853 return OPVXX2(60, 488, 0)
4854 case AXVCVUXWDP:
4855 return OPVXX2(60, 232, 0)
4856 case AXVCVSXDSP:
4857 return OPVXX2(60, 440, 0)
4858 case AXVCVSXWSP:
4859 return OPVXX2(60, 184, 0)
4860 case AXVCVUXDSP:
4861 return OPVXX2(60, 424, 0)
4862 case AXVCVUXWSP:
4863 return OPVXX2(60, 168, 0)
4864
4865
4866 case AMADDHD:
4867 return OPVX(4, 48, 0, 0)
4868 case AMADDHDU:
4869 return OPVX(4, 49, 0, 0)
4870 case AMADDLD:
4871 return OPVX(4, 51, 0, 0)
4872
4873 case AXOR:
4874 return OPVCC(31, 316, 0, 0)
4875 case AXORCC:
4876 return OPVCC(31, 316, 0, 1)
4877 }
4878
4879 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
4880 return 0
4881 }
4882
4883 func (c *ctxt9) opirrr(a obj.As) uint32 {
4884 switch a {
4885
4886
4887
4888 case AVSLDOI:
4889 return OPVX(4, 44, 0, 0)
4890 }
4891
4892 c.ctxt.Diag("bad i/r/r/r opcode %v", a)
4893 return 0
4894 }
4895
4896 func (c *ctxt9) opiirr(a obj.As) uint32 {
4897 switch a {
4898
4899
4900 case AVSHASIGMAW:
4901 return OPVX(4, 1666, 0, 0)
4902 case AVSHASIGMAD:
4903 return OPVX(4, 1730, 0, 0)
4904 }
4905
4906 c.ctxt.Diag("bad i/i/r/r opcode %v", a)
4907 return 0
4908 }
4909
4910 func (c *ctxt9) opirr(a obj.As) uint32 {
4911 switch a {
4912 case AADD:
4913 return OPVCC(14, 0, 0, 0)
4914 case AADDC:
4915 return OPVCC(12, 0, 0, 0)
4916 case AADDCCC:
4917 return OPVCC(13, 0, 0, 0)
4918 case AADDIS:
4919 return OPVCC(15, 0, 0, 0)
4920
4921 case AANDCC:
4922 return OPVCC(28, 0, 0, 0)
4923 case AANDISCC:
4924 return OPVCC(29, 0, 0, 0)
4925
4926 case ABR:
4927 return OPVCC(18, 0, 0, 0)
4928 case ABL:
4929 return OPVCC(18, 0, 0, 0) | 1
4930 case obj.ADUFFZERO:
4931 return OPVCC(18, 0, 0, 0) | 1
4932 case obj.ADUFFCOPY:
4933 return OPVCC(18, 0, 0, 0) | 1
4934 case ABC:
4935 return OPVCC(16, 0, 0, 0)
4936 case ABCL:
4937 return OPVCC(16, 0, 0, 0) | 1
4938
4939 case ABEQ:
4940 return AOP_RRR(16<<26, BO_BCR, BI_EQ, 0)
4941 case ABGE:
4942 return AOP_RRR(16<<26, BO_NOTBCR, BI_LT, 0)
4943 case ABGT:
4944 return AOP_RRR(16<<26, BO_BCR, BI_GT, 0)
4945 case ABLE:
4946 return AOP_RRR(16<<26, BO_NOTBCR, BI_GT, 0)
4947 case ABLT:
4948 return AOP_RRR(16<<26, BO_BCR, BI_LT, 0)
4949 case ABNE:
4950 return AOP_RRR(16<<26, BO_NOTBCR, BI_EQ, 0)
4951 case ABVC:
4952 return AOP_RRR(16<<26, BO_NOTBCR, BI_FU, 0)
4953 case ABVS:
4954 return AOP_RRR(16<<26, BO_BCR, BI_FU, 0)
4955 case ABDZ:
4956 return AOP_RRR(16<<26, BO_NOTBCTR, 0, 0)
4957 case ABDNZ:
4958 return AOP_RRR(16<<26, BO_BCTR, 0, 0)
4959
4960 case ACMP:
4961 return OPVCC(11, 0, 0, 0) | 1<<21
4962 case ACMPU:
4963 return OPVCC(10, 0, 0, 0) | 1<<21
4964 case ACMPW:
4965 return OPVCC(11, 0, 0, 0)
4966 case ACMPWU:
4967 return OPVCC(10, 0, 0, 0)
4968 case ACMPEQB:
4969 return OPVCC(31, 224, 0, 0)
4970
4971 case ALSW:
4972 return OPVCC(31, 597, 0, 0)
4973
4974 case ACOPY:
4975 return OPVCC(31, 774, 0, 0)
4976 case APASTECC:
4977 return OPVCC(31, 902, 0, 1)
4978 case ADARN:
4979 return OPVCC(31, 755, 0, 0)
4980
4981 case AMULLW, AMULLD:
4982 return OPVCC(7, 0, 0, 0)
4983
4984 case AOR:
4985 return OPVCC(24, 0, 0, 0)
4986 case AORIS:
4987 return OPVCC(25, 0, 0, 0)
4988
4989 case ARLWMI:
4990 return OPVCC(20, 0, 0, 0)
4991 case ARLWMICC:
4992 return OPVCC(20, 0, 0, 1)
4993 case ARLDMI:
4994 return OPMD(30, 3, 0)
4995 case ARLDMICC:
4996 return OPMD(30, 3, 1)
4997 case ARLDIMI:
4998 return OPMD(30, 3, 0)
4999 case ARLDIMICC:
5000 return OPMD(30, 3, 1)
5001 case ARLWNM:
5002 return OPVCC(21, 0, 0, 0)
5003 case ARLWNMCC:
5004 return OPVCC(21, 0, 0, 1)
5005
5006 case ARLDCL:
5007 return OPMD(30, 0, 0)
5008 case ARLDCLCC:
5009 return OPMD(30, 0, 1)
5010 case ARLDCR:
5011 return OPMD(30, 1, 0)
5012 case ARLDCRCC:
5013 return OPMD(30, 1, 1)
5014 case ARLDC:
5015 return OPMD(30, 2, 0)
5016 case ARLDCCC:
5017 return OPMD(30, 2, 1)
5018
5019 case ASRAW:
5020 return OPVCC(31, 824, 0, 0)
5021 case ASRAWCC:
5022 return OPVCC(31, 824, 0, 1)
5023 case ASRAD:
5024 return OPVCC(31, (413 << 1), 0, 0)
5025 case ASRADCC:
5026 return OPVCC(31, (413 << 1), 0, 1)
5027 case AEXTSWSLI:
5028 return OPVCC(31, 445, 0, 0)
5029 case AEXTSWSLICC:
5030 return OPVCC(31, 445, 0, 1)
5031
5032 case ASTSW:
5033 return OPVCC(31, 725, 0, 0)
5034
5035 case ASUBC:
5036 return OPVCC(8, 0, 0, 0)
5037
5038 case ATW:
5039 return OPVCC(3, 0, 0, 0)
5040 case ATD:
5041 return OPVCC(2, 0, 0, 0)
5042
5043
5044
5045
5046 case AVSPLTB:
5047 return OPVX(4, 524, 0, 0)
5048 case AVSPLTH:
5049 return OPVX(4, 588, 0, 0)
5050 case AVSPLTW:
5051 return OPVX(4, 652, 0, 0)
5052
5053 case AVSPLTISB:
5054 return OPVX(4, 780, 0, 0)
5055 case AVSPLTISH:
5056 return OPVX(4, 844, 0, 0)
5057 case AVSPLTISW:
5058 return OPVX(4, 908, 0, 0)
5059
5060
5061 case AFTDIV:
5062 return OPVCC(63, 128, 0, 0)
5063 case AFTSQRT:
5064 return OPVCC(63, 160, 0, 0)
5065
5066 case AXOR:
5067 return OPVCC(26, 0, 0, 0)
5068 case AXORIS:
5069 return OPVCC(27, 0, 0, 0)
5070 }
5071
5072 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
5073 return 0
5074 }
5075
5076
5079 func (c *ctxt9) opload(a obj.As) uint32 {
5080 switch a {
5081 case AMOVD:
5082 return OPVCC(58, 0, 0, 0)
5083 case AMOVDU:
5084 return OPVCC(58, 0, 0, 1)
5085 case AMOVWZ:
5086 return OPVCC(32, 0, 0, 0)
5087 case AMOVWZU:
5088 return OPVCC(33, 0, 0, 0)
5089 case AMOVW:
5090 return OPVCC(58, 0, 0, 0) | 1<<1
5091 case ALXV:
5092 return OPDQ(61, 1, 0)
5093 case ALXVL:
5094 return OPVXX1(31, 269, 0)
5095 case ALXVLL:
5096 return OPVXX1(31, 301, 0)
5097 case ALXVX:
5098 return OPVXX1(31, 268, 0)
5099
5100
5101 case AMOVB, AMOVBZ:
5102 return OPVCC(34, 0, 0, 0)
5103
5104
5105 case AMOVBU, AMOVBZU:
5106 return OPVCC(35, 0, 0, 0)
5107 case AFMOVD:
5108 return OPVCC(50, 0, 0, 0)
5109 case AFMOVDU:
5110 return OPVCC(51, 0, 0, 0)
5111 case AFMOVS:
5112 return OPVCC(48, 0, 0, 0)
5113 case AFMOVSU:
5114 return OPVCC(49, 0, 0, 0)
5115 case AMOVH:
5116 return OPVCC(42, 0, 0, 0)
5117 case AMOVHU:
5118 return OPVCC(43, 0, 0, 0)
5119 case AMOVHZ:
5120 return OPVCC(40, 0, 0, 0)
5121 case AMOVHZU:
5122 return OPVCC(41, 0, 0, 0)
5123 case AMOVMW:
5124 return OPVCC(46, 0, 0, 0)
5125 }
5126
5127 c.ctxt.Diag("bad load opcode %v", a)
5128 return 0
5129 }
5130
5131
5134 func (c *ctxt9) oploadx(a obj.As) uint32 {
5135 switch a {
5136 case AMOVWZ:
5137 return OPVCC(31, 23, 0, 0)
5138 case AMOVWZU:
5139 return OPVCC(31, 55, 0, 0)
5140 case AMOVW:
5141 return OPVCC(31, 341, 0, 0)
5142 case AMOVWU:
5143 return OPVCC(31, 373, 0, 0)
5144
5145 case AMOVB, AMOVBZ:
5146 return OPVCC(31, 87, 0, 0)
5147
5148 case AMOVBU, AMOVBZU:
5149 return OPVCC(31, 119, 0, 0)
5150 case AFMOVD:
5151 return OPVCC(31, 599, 0, 0)
5152 case AFMOVDU:
5153 return OPVCC(31, 631, 0, 0)
5154 case AFMOVS:
5155 return OPVCC(31, 535, 0, 0)
5156 case AFMOVSU:
5157 return OPVCC(31, 567, 0, 0)
5158 case AFMOVSX:
5159 return OPVCC(31, 855, 0, 0)
5160 case AFMOVSZ:
5161 return OPVCC(31, 887, 0, 0)
5162 case AMOVH:
5163 return OPVCC(31, 343, 0, 0)
5164 case AMOVHU:
5165 return OPVCC(31, 375, 0, 0)
5166 case AMOVHBR:
5167 return OPVCC(31, 790, 0, 0)
5168 case AMOVWBR:
5169 return OPVCC(31, 534, 0, 0)
5170 case AMOVDBR:
5171 return OPVCC(31, 532, 0, 0)
5172 case AMOVHZ:
5173 return OPVCC(31, 279, 0, 0)
5174 case AMOVHZU:
5175 return OPVCC(31, 311, 0, 0)
5176 case ALBAR:
5177 return OPVCC(31, 52, 0, 0)
5178 case ALHAR:
5179 return OPVCC(31, 116, 0, 0)
5180 case ALWAR:
5181 return OPVCC(31, 20, 0, 0)
5182 case ALDAR:
5183 return OPVCC(31, 84, 0, 0)
5184 case ALSW:
5185 return OPVCC(31, 533, 0, 0)
5186 case AMOVD:
5187 return OPVCC(31, 21, 0, 0)
5188 case AMOVDU:
5189 return OPVCC(31, 53, 0, 0)
5190
5191
5192 case ALVEBX:
5193 return OPVCC(31, 7, 0, 0)
5194 case ALVEHX:
5195 return OPVCC(31, 39, 0, 0)
5196 case ALVEWX:
5197 return OPVCC(31, 71, 0, 0)
5198 case ALVX:
5199 return OPVCC(31, 103, 0, 0)
5200 case ALVXL:
5201 return OPVCC(31, 359, 0, 0)
5202 case ALVSL:
5203 return OPVCC(31, 6, 0, 0)
5204 case ALVSR:
5205 return OPVCC(31, 38, 0, 0)
5206
5207
5208
5209 case ALXVX:
5210 return OPVXX1(31, 268, 0)
5211 case ALXVD2X:
5212 return OPVXX1(31, 844, 0)
5213 case ALXVW4X:
5214 return OPVXX1(31, 780, 0)
5215 case ALXVH8X:
5216 return OPVXX1(31, 812, 0)
5217 case ALXVB16X:
5218 return OPVXX1(31, 876, 0)
5219 case ALXVDSX:
5220 return OPVXX1(31, 332, 0)
5221 case ALXSDX:
5222 return OPVXX1(31, 588, 0)
5223 case ALXSIWAX:
5224 return OPVXX1(31, 76, 0)
5225 case ALXSIWZX:
5226 return OPVXX1(31, 12, 0)
5227 }
5228
5229 c.ctxt.Diag("bad loadx opcode %v", a)
5230 return 0
5231 }
5232
5233
5236 func (c *ctxt9) opstore(a obj.As) uint32 {
5237 switch a {
5238 case AMOVB, AMOVBZ:
5239 return OPVCC(38, 0, 0, 0)
5240
5241 case AMOVBU, AMOVBZU:
5242 return OPVCC(39, 0, 0, 0)
5243 case AFMOVD:
5244 return OPVCC(54, 0, 0, 0)
5245 case AFMOVDU:
5246 return OPVCC(55, 0, 0, 0)
5247 case AFMOVS:
5248 return OPVCC(52, 0, 0, 0)
5249 case AFMOVSU:
5250 return OPVCC(53, 0, 0, 0)
5251
5252 case AMOVHZ, AMOVH:
5253 return OPVCC(44, 0, 0, 0)
5254
5255 case AMOVHZU, AMOVHU:
5256 return OPVCC(45, 0, 0, 0)
5257 case AMOVMW:
5258 return OPVCC(47, 0, 0, 0)
5259 case ASTSW:
5260 return OPVCC(31, 725, 0, 0)
5261
5262 case AMOVWZ, AMOVW:
5263 return OPVCC(36, 0, 0, 0)
5264
5265 case AMOVWZU, AMOVWU:
5266 return OPVCC(37, 0, 0, 0)
5267 case AMOVD:
5268 return OPVCC(62, 0, 0, 0)
5269 case AMOVDU:
5270 return OPVCC(62, 0, 0, 1)
5271 case ASTXV:
5272 return OPDQ(61, 5, 0)
5273 case ASTXVL:
5274 return OPVXX1(31, 397, 0)
5275 case ASTXVLL:
5276 return OPVXX1(31, 429, 0)
5277 case ASTXVX:
5278 return OPVXX1(31, 396, 0)
5279
5280 }
5281
5282 c.ctxt.Diag("unknown store opcode %v", a)
5283 return 0
5284 }
5285
5286
5289 func (c *ctxt9) opstorex(a obj.As) uint32 {
5290 switch a {
5291 case AMOVB, AMOVBZ:
5292 return OPVCC(31, 215, 0, 0)
5293
5294 case AMOVBU, AMOVBZU:
5295 return OPVCC(31, 247, 0, 0)
5296 case AFMOVD:
5297 return OPVCC(31, 727, 0, 0)
5298 case AFMOVDU:
5299 return OPVCC(31, 759, 0, 0)
5300 case AFMOVS:
5301 return OPVCC(31, 663, 0, 0)
5302 case AFMOVSU:
5303 return OPVCC(31, 695, 0, 0)
5304 case AFMOVSX:
5305 return OPVCC(31, 983, 0, 0)
5306
5307 case AMOVHZ, AMOVH:
5308 return OPVCC(31, 407, 0, 0)
5309 case AMOVHBR:
5310 return OPVCC(31, 918, 0, 0)
5311
5312 case AMOVHZU, AMOVHU:
5313 return OPVCC(31, 439, 0, 0)
5314
5315 case AMOVWZ, AMOVW:
5316 return OPVCC(31, 151, 0, 0)
5317
5318 case AMOVWZU, AMOVWU:
5319 return OPVCC(31, 183, 0, 0)
5320 case ASTSW:
5321 return OPVCC(31, 661, 0, 0)
5322 case AMOVWBR:
5323 return OPVCC(31, 662, 0, 0)
5324 case AMOVDBR:
5325 return OPVCC(31, 660, 0, 0)
5326 case ASTBCCC:
5327 return OPVCC(31, 694, 0, 1)
5328 case ASTHCCC:
5329 return OPVCC(31, 726, 0, 1)
5330 case ASTWCCC:
5331 return OPVCC(31, 150, 0, 1)
5332 case ASTDCCC:
5333 return OPVCC(31, 214, 0, 1)
5334 case AMOVD:
5335 return OPVCC(31, 149, 0, 0)
5336 case AMOVDU:
5337 return OPVCC(31, 181, 0, 0)
5338
5339
5340 case ASTVEBX:
5341 return OPVCC(31, 135, 0, 0)
5342 case ASTVEHX:
5343 return OPVCC(31, 167, 0, 0)
5344 case ASTVEWX:
5345 return OPVCC(31, 199, 0, 0)
5346 case ASTVX:
5347 return OPVCC(31, 231, 0, 0)
5348 case ASTVXL:
5349 return OPVCC(31, 487, 0, 0)
5350
5351
5352
5353 case ASTXVX:
5354 return OPVXX1(31, 396, 0)
5355 case ASTXVD2X:
5356 return OPVXX1(31, 972, 0)
5357 case ASTXVW4X:
5358 return OPVXX1(31, 908, 0)
5359 case ASTXVH8X:
5360 return OPVXX1(31, 940, 0)
5361 case ASTXVB16X:
5362 return OPVXX1(31, 1004, 0)
5363
5364 case ASTXSDX:
5365 return OPVXX1(31, 716, 0)
5366
5367 case ASTXSIWX:
5368 return OPVXX1(31, 140, 0)
5369
5370
5371
5372 }
5373
5374 c.ctxt.Diag("unknown storex opcode %v", a)
5375 return 0
5376 }
5377
View as plain text