a.out.go

     1  // cmd/9c/9.out.h from Vita Nuova.
     2  //
     3  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     4  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     5  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     6  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     7  //	Portions Copyright © 2004,2006 Bruce Ellis
     8  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     9  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
    10  //	Portions Copyright © 2009 The Go Authors. All rights reserved.
    11  //
    12  // Permission is hereby granted, free of charge, to any person obtaining a copy
    13  // of this software and associated documentation files (the "Software"), to deal
    14  // in the Software without restriction, including without limitation the rights
    15  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    16  // copies of the Software, and to permit persons to whom the Software is
    17  // furnished to do so, subject to the following conditions:
    18  //
    19  // The above copyright notice and this permission notice shall be included in
    20  // all copies or substantial portions of the Software.
    21  //
    22  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    23  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    24  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    25  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    26  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    27  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    28  // THE SOFTWARE.
    29  
    30  package ppc64
    31  
    32  import "cmd/internal/obj"
    33  
    34  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64
    35  
    36  /*
    37   * powerpc 64
    38   */
    39  const (
    40  	NSNAME = 8
    41  	NSYM   = 50
    42  	NREG   = 32 /* number of general registers */
    43  	NFREG  = 32 /* number of floating point registers */
    44  )
    45  
    46  const (
    47  	/* RBasePPC64 = 4096 */
    48  	/* R0=4096 ... R31=4127 */
    49  	REG_R0 = obj.RBasePPC64 + iota
    50  	REG_R1
    51  	REG_R2
    52  	REG_R3
    53  	REG_R4
    54  	REG_R5
    55  	REG_R6
    56  	REG_R7
    57  	REG_R8
    58  	REG_R9
    59  	REG_R10
    60  	REG_R11
    61  	REG_R12
    62  	REG_R13
    63  	REG_R14
    64  	REG_R15
    65  	REG_R16
    66  	REG_R17
    67  	REG_R18
    68  	REG_R19
    69  	REG_R20
    70  	REG_R21
    71  	REG_R22
    72  	REG_R23
    73  	REG_R24
    74  	REG_R25
    75  	REG_R26
    76  	REG_R27
    77  	REG_R28
    78  	REG_R29
    79  	REG_R30
    80  	REG_R31
    81  
    82  	// CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32
    83  	REG_CR0LT
    84  	REG_CR0GT
    85  	REG_CR0EQ
    86  	REG_CR0SO
    87  	REG_CR1LT
    88  	REG_CR1GT
    89  	REG_CR1EQ
    90  	REG_CR1SO
    91  	REG_CR2LT
    92  	REG_CR2GT
    93  	REG_CR2EQ
    94  	REG_CR2SO
    95  	REG_CR3LT
    96  	REG_CR3GT
    97  	REG_CR3EQ
    98  	REG_CR3SO
    99  	REG_CR4LT
   100  	REG_CR4GT
   101  	REG_CR4EQ
   102  	REG_CR4SO
   103  	REG_CR5LT
   104  	REG_CR5GT
   105  	REG_CR5EQ
   106  	REG_CR5SO
   107  	REG_CR6LT
   108  	REG_CR6GT
   109  	REG_CR6EQ
   110  	REG_CR6SO
   111  	REG_CR7LT
   112  	REG_CR7GT
   113  	REG_CR7EQ
   114  	REG_CR7SO
   115  
   116  	/* Align FPR and VSR vectors such that when masked with 0x3F they produce
   117  	   an equivalent VSX register. */
   118  	/* F0=4160 ... F31=4191 */
   119  	REG_F0
   120  	REG_F1
   121  	REG_F2
   122  	REG_F3
   123  	REG_F4
   124  	REG_F5
   125  	REG_F6
   126  	REG_F7
   127  	REG_F8
   128  	REG_F9
   129  	REG_F10
   130  	REG_F11
   131  	REG_F12
   132  	REG_F13
   133  	REG_F14
   134  	REG_F15
   135  	REG_F16
   136  	REG_F17
   137  	REG_F18
   138  	REG_F19
   139  	REG_F20
   140  	REG_F21
   141  	REG_F22
   142  	REG_F23
   143  	REG_F24
   144  	REG_F25
   145  	REG_F26
   146  	REG_F27
   147  	REG_F28
   148  	REG_F29
   149  	REG_F30
   150  	REG_F31
   151  
   152  	/* V0=4192 ... V31=4223 */
   153  	REG_V0
   154  	REG_V1
   155  	REG_V2
   156  	REG_V3
   157  	REG_V4
   158  	REG_V5
   159  	REG_V6
   160  	REG_V7
   161  	REG_V8
   162  	REG_V9
   163  	REG_V10
   164  	REG_V11
   165  	REG_V12
   166  	REG_V13
   167  	REG_V14
   168  	REG_V15
   169  	REG_V16
   170  	REG_V17
   171  	REG_V18
   172  	REG_V19
   173  	REG_V20
   174  	REG_V21
   175  	REG_V22
   176  	REG_V23
   177  	REG_V24
   178  	REG_V25
   179  	REG_V26
   180  	REG_V27
   181  	REG_V28
   182  	REG_V29
   183  	REG_V30
   184  	REG_V31
   185  
   186  	/* VS0=4224 ... VS63=4287 */
   187  	REG_VS0
   188  	REG_VS1
   189  	REG_VS2
   190  	REG_VS3
   191  	REG_VS4
   192  	REG_VS5
   193  	REG_VS6
   194  	REG_VS7
   195  	REG_VS8
   196  	REG_VS9
   197  	REG_VS10
   198  	REG_VS11
   199  	REG_VS12
   200  	REG_VS13
   201  	REG_VS14
   202  	REG_VS15
   203  	REG_VS16
   204  	REG_VS17
   205  	REG_VS18
   206  	REG_VS19
   207  	REG_VS20
   208  	REG_VS21
   209  	REG_VS22
   210  	REG_VS23
   211  	REG_VS24
   212  	REG_VS25
   213  	REG_VS26
   214  	REG_VS27
   215  	REG_VS28
   216  	REG_VS29
   217  	REG_VS30
   218  	REG_VS31
   219  	REG_VS32
   220  	REG_VS33
   221  	REG_VS34
   222  	REG_VS35
   223  	REG_VS36
   224  	REG_VS37
   225  	REG_VS38
   226  	REG_VS39
   227  	REG_VS40
   228  	REG_VS41
   229  	REG_VS42
   230  	REG_VS43
   231  	REG_VS44
   232  	REG_VS45
   233  	REG_VS46
   234  	REG_VS47
   235  	REG_VS48
   236  	REG_VS49
   237  	REG_VS50
   238  	REG_VS51
   239  	REG_VS52
   240  	REG_VS53
   241  	REG_VS54
   242  	REG_VS55
   243  	REG_VS56
   244  	REG_VS57
   245  	REG_VS58
   246  	REG_VS59
   247  	REG_VS60
   248  	REG_VS61
   249  	REG_VS62
   250  	REG_VS63
   251  
   252  	REG_CR0
   253  	REG_CR1
   254  	REG_CR2
   255  	REG_CR3
   256  	REG_CR4
   257  	REG_CR5
   258  	REG_CR6
   259  	REG_CR7
   260  
   261  	// MMA accumulator registers, these shadow VSR 0-31
   262  	// e.g MMAx shadows VSRx*4-VSRx*4+3 or
   263  	//     MMA0 shadows VSR0-VSR3
   264  	REG_A0
   265  	REG_A1
   266  	REG_A2
   267  	REG_A3
   268  	REG_A4
   269  	REG_A5
   270  	REG_A6
   271  	REG_A7
   272  
   273  	REG_MSR
   274  	REG_FPSCR
   275  	REG_CR
   276  
   277  	REG_SPECIAL = REG_CR0
   278  
   279  	REG_CRBIT0 = REG_CR0LT // An alias for a Condition Register bit 0
   280  
   281  	REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers
   282  
   283  	REG_XER = REG_SPR0 + 1
   284  	REG_LR  = REG_SPR0 + 8
   285  	REG_CTR = REG_SPR0 + 9
   286  
   287  	REGZERO = REG_R0 /* set to zero */
   288  	REGSP   = REG_R1
   289  	REGSB   = REG_R2
   290  	REGRET  = REG_R3
   291  	REGARG  = -1      /* -1 disables passing the first argument in register */
   292  	REGRT1  = REG_R20 /* reserved for runtime, duffzero and duffcopy */
   293  	REGRT2  = REG_R21 /* reserved for runtime, duffcopy */
   294  	REGMIN  = REG_R7  /* register variables allocated from here to REGMAX */
   295  	REGCTXT = REG_R11 /* context for closures */
   296  	REGTLS  = REG_R13 /* C ABI TLS base pointer */
   297  	REGMAX  = REG_R27
   298  	REGEXT  = REG_R30 /* external registers allocated from here down */
   299  	REGG    = REG_R30 /* G */
   300  	REGTMP  = REG_R31 /* used by the linker */
   301  	FREGRET = REG_F0
   302  	FREGMIN = REG_F17 /* first register variable */
   303  	FREGMAX = REG_F26 /* last register variable for 9g only */
   304  	FREGEXT = REG_F26 /* first external register */
   305  )
   306  
   307  // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI
   308  // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture
   309  var PPC64DWARFRegisters = map[int16]int16{}
   310  
   311  func init() {
   312  	// f assigns dwarfregister[from:to] = (base):(to-from+base)
   313  	f := func(from, to, base int16) {
   314  		for r := int16(from); r <= to; r++ {
   315  			PPC64DWARFRegisters[r] = r - from + base
   316  		}
   317  	}
   318  	f(REG_R0, REG_R31, 0)
   319  	f(REG_F0, REG_F31, 32)
   320  	f(REG_V0, REG_V31, 77)
   321  	f(REG_CR0, REG_CR7, 68)
   322  
   323  	f(REG_VS0, REG_VS31, 32)  // overlaps F0-F31
   324  	f(REG_VS32, REG_VS63, 77) // overlaps V0-V31
   325  	PPC64DWARFRegisters[REG_LR] = 65
   326  	PPC64DWARFRegisters[REG_CTR] = 66
   327  	PPC64DWARFRegisters[REG_XER] = 76
   328  }
   329  
   330  /*
   331   * GENERAL:
   332   *
   333   * compiler allocates R3 up as temps
   334   * compiler allocates register variables R7-R27
   335   * compiler allocates external registers R30 down
   336   *
   337   * compiler allocates register variables F17-F26
   338   * compiler allocates external registers F26 down
   339   */
   340  const (
   341  	BIG = 32768 - 8
   342  )
   343  
   344  const (
   345  	/* mark flags */
   346  	LABEL    = 1 << 0
   347  	LEAF     = 1 << 1
   348  	FLOAT    = 1 << 2
   349  	BRANCH   = 1 << 3
   350  	LOAD     = 1 << 4
   351  	FCMP     = 1 << 5
   352  	SYNC     = 1 << 6
   353  	LIST     = 1 << 7
   354  	FOLL     = 1 << 8
   355  	NOSCHED  = 1 << 9
   356  	PFX_X64B = 1 << 10 // A prefixed instruction crossing a 64B boundary
   357  )
   358  
   359  // Values for use in branch instruction BC
   360  // BC B0,BI,label
   361  // BO is type of branch + likely bits described below
   362  // BI is CR value + branch type
   363  // ex: BEQ CR2,label is BC 12,10,label
   364  //   12 = BO_BCR
   365  //   10 = BI_CR2 + BI_EQ
   366  
   367  const (
   368  	BI_CR0 = 0
   369  	BI_CR1 = 4
   370  	BI_CR2 = 8
   371  	BI_CR3 = 12
   372  	BI_CR4 = 16
   373  	BI_CR5 = 20
   374  	BI_CR6 = 24
   375  	BI_CR7 = 28
   376  	BI_LT  = 0
   377  	BI_GT  = 1
   378  	BI_EQ  = 2
   379  	BI_FU  = 3
   380  )
   381  
   382  // Common values for the BO field.
   383  
   384  const (
   385  	BO_ALWAYS  = 20 // branch unconditionally
   386  	BO_BCTR    = 16 // decrement ctr, branch on ctr != 0
   387  	BO_NOTBCTR = 18 // decrement ctr, branch on ctr == 0
   388  	BO_BCR     = 12 // branch on cr value
   389  	BO_BCRBCTR = 8  // decrement ctr, branch on ctr != 0 and cr value
   390  	BO_NOTBCR  = 4  // branch on not cr value
   391  )
   392  
   393  // Bit settings from the CR
   394  
   395  const (
   396  	C_COND_LT = iota // 0 result is negative
   397  	C_COND_GT        // 1 result is positive
   398  	C_COND_EQ        // 2 result is zero
   399  	C_COND_SO        // 3 summary overflow or FP compare w/ NaN
   400  )
   401  
   402  //go:generate go run ../mkcnames.go -i a.out.go -o anames9.go -p ppc64
   403  const (
   404  	C_NONE     = iota
   405  	C_REGP     /* An even numbered gpr which can be used a gpr pair argument */
   406  	C_REG      /* Any gpr register */
   407  	C_FREGP    /* An even numbered fpr which can be used a fpr pair argument */
   408  	C_FREG     /* Any fpr register */
   409  	C_VREG     /* Any vector register */
   410  	C_VSREGP   /* An even numbered vsx register which can be used as a vsx register pair argument */
   411  	C_VSREG    /* Any vector-scalar register */
   412  	C_CREG     /* The condition registor (CR) */
   413  	C_CRBIT    /* A single bit of the CR register (0-31) */
   414  	C_SPR      /* special processor register */
   415  	C_AREG     /* MMA accumulator register */
   416  	C_ZCON     /* The constant zero */
   417  	C_U1CON    /* 1 bit unsigned constant */
   418  	C_U2CON    /* 2 bit unsigned constant */
   419  	C_U3CON    /* 3 bit unsigned constant */
   420  	C_U4CON    /* 4 bit unsigned constant */
   421  	C_U5CON    /* 5 bit unsigned constant */
   422  	C_U8CON    /* 8 bit unsigned constant */
   423  	C_U15CON   /* 15 bit unsigned constant */
   424  	C_S16CON   /* 16 bit signed constant */
   425  	C_U16CON   /* 16 bit unsigned constant */
   426  	C_16CON    /* Any constant which fits into 16 bits. Can be signed or unsigned */
   427  	C_U31CON   /* 31 bit unsigned constant */
   428  	C_S32CON   /* 32 bit signed constant */
   429  	C_U32CON   /* 32 bit unsigned constant */
   430  	C_32CON    /* Any constant which fits into 32 bits. Can be signed or unsigned */
   431  	C_S34CON   /* 34 bit signed constant */
   432  	C_64CON    /* Any constant which fits into 64 bits. Can be signed or unsigned */
   433  	C_SACON    /* $n(REG) where n <= int16 */
   434  	C_LACON    /* $n(REG) where n <= int32 */
   435  	C_DACON    /* $n(REG) where n <= int64 */
   436  	C_BRA      /* A short offset argument to a branching instruction */
   437  	C_BRAPIC   /* Like C_BRA, but requires an extra NOP for potential TOC restore by the linker. */
   438  	C_ZOREG    /* An $0+reg memory op */
   439  	C_SOREG    /* An $n+reg memory arg where n is a 16 bit signed offset */
   440  	C_LOREG    /* An $n+reg memory arg where n is a 32 bit signed offset */
   441  	C_XOREG    /* An reg+reg memory arg */
   442  	C_FPSCR    /* The fpscr register */
   443  	C_LR       /* The link register */
   444  	C_CTR      /* The count register */
   445  	C_ANY      /* Any argument */
   446  	C_GOK      /* A non-matched argument */
   447  	C_ADDR     /* A symbolic memory location */
   448  	C_TLS_LE   /* A thread local, local-exec, type memory arg */
   449  	C_TLS_IE   /* A thread local, initial-exec, type memory arg */
   450  	C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */
   451  
   452  	C_NCLASS /* must be the last */
   453  )
   454  
   455  const (
   456  	AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota
   457  	AADDCC
   458  	AADDIS
   459  	AADDV
   460  	AADDVCC
   461  	AADDC
   462  	AADDCCC
   463  	AADDCV
   464  	AADDCVCC
   465  	AADDME
   466  	AADDMECC
   467  	AADDMEVCC
   468  	AADDMEV
   469  	AADDE
   470  	AADDECC
   471  	AADDEVCC
   472  	AADDEV
   473  	AADDZE
   474  	AADDZECC
   475  	AADDZEVCC
   476  	AADDZEV
   477  	AADDEX
   478  	AAND
   479  	AANDCC
   480  	AANDN
   481  	AANDNCC
   482  	AANDISCC
   483  	ABC
   484  	ABCL
   485  	ABEQ
   486  	ABGE // not LT = G/E/U
   487  	ABGT
   488  	ABLE // not GT = L/E/U
   489  	ABLT
   490  	ABNE  // not EQ = L/G/U
   491  	ABVC  // Branch if float not unordered (also branch on not summary overflow)
   492  	ABVS  // Branch if float unordered (also branch on summary overflow)
   493  	ABDNZ // Decrement CTR, and branch if CTR != 0
   494  	ABDZ  // Decrement CTR, and branch if CTR == 0
   495  	ACMP
   496  	ACMPU
   497  	ACMPEQB
   498  	ACNTLZW
   499  	ACNTLZWCC
   500  	ACRAND
   501  	ACRANDN
   502  	ACREQV
   503  	ACRNAND
   504  	ACRNOR
   505  	ACROR
   506  	ACRORN
   507  	ACRXOR
   508  	ADADD
   509  	ADADDQ
   510  	ADCMPO
   511  	ADCMPOQ
   512  	ADCMPU
   513  	ADCMPUQ
   514  	ADDIV
   515  	ADDIVQ
   516  	ADIVW
   517  	ADIVWCC
   518  	ADIVWVCC
   519  	ADIVWV
   520  	ADIVWU
   521  	ADIVWUCC
   522  	ADIVWUVCC
   523  	ADIVWUV
   524  	ADMUL
   525  	ADMULQ
   526  	ADSUB
   527  	ADSUBQ
   528  	AMODUD
   529  	AMODUW
   530  	AMODSD
   531  	AMODSW
   532  	AEQV
   533  	AEQVCC
   534  	AEXTSB
   535  	AEXTSBCC
   536  	AEXTSH
   537  	AEXTSHCC
   538  	AFABS
   539  	AFABSCC
   540  	AFADD
   541  	AFADDCC
   542  	AFADDS
   543  	AFADDSCC
   544  	AFCMPO
   545  	AFCMPU
   546  	AFCTIW
   547  	AFCTIWCC
   548  	AFCTIWZ
   549  	AFCTIWZCC
   550  	AFDIV
   551  	AFDIVCC
   552  	AFDIVS
   553  	AFDIVSCC
   554  	AFMADD
   555  	AFMADDCC
   556  	AFMADDS
   557  	AFMADDSCC
   558  	AFMOVD
   559  	AFMOVDCC
   560  	AFMOVDU
   561  	AFMOVS
   562  	AFMOVSU
   563  	AFMOVSX
   564  	AFMOVSZ
   565  	AFMSUB
   566  	AFMSUBCC
   567  	AFMSUBS
   568  	AFMSUBSCC
   569  	AFMUL
   570  	AFMULCC
   571  	AFMULS
   572  	AFMULSCC
   573  	AFNABS
   574  	AFNABSCC
   575  	AFNEG
   576  	AFNEGCC
   577  	AFNMADD
   578  	AFNMADDCC
   579  	AFNMADDS
   580  	AFNMADDSCC
   581  	AFNMSUB
   582  	AFNMSUBCC
   583  	AFNMSUBS
   584  	AFNMSUBSCC
   585  	AFRSP
   586  	AFRSPCC
   587  	AFSUB
   588  	AFSUBCC
   589  	AFSUBS
   590  	AFSUBSCC
   591  	AISEL
   592  	AMOVMW
   593  	ALBAR
   594  	ALHAR
   595  	ALSW
   596  	ALWAR
   597  	ALWSYNC
   598  	AMOVDBR
   599  	AMOVWBR
   600  	AMOVB
   601  	AMOVBU
   602  	AMOVBZ
   603  	AMOVBZU
   604  	AMOVH
   605  	AMOVHBR
   606  	AMOVHU
   607  	AMOVHZ
   608  	AMOVHZU
   609  	AMOVW
   610  	AMOVWU
   611  	AMOVFL
   612  	AMOVCRFS
   613  	AMTFSB0
   614  	AMTFSB0CC
   615  	AMTFSB1
   616  	AMTFSB1CC
   617  	AMULHW
   618  	AMULHWCC
   619  	AMULHWU
   620  	AMULHWUCC
   621  	AMULLW
   622  	AMULLWCC
   623  	AMULLWVCC
   624  	AMULLWV
   625  	ANAND
   626  	ANANDCC
   627  	ANEG
   628  	ANEGCC
   629  	ANEGVCC
   630  	ANEGV
   631  	ANOR
   632  	ANORCC
   633  	AOR
   634  	AORCC
   635  	AORN
   636  	AORNCC
   637  	AORIS
   638  	AREM
   639  	AREMU
   640  	ARFI
   641  	ARLWMI
   642  	ARLWMICC
   643  	ARLWNM
   644  	ARLWNMCC
   645  	ACLRLSLWI
   646  	ASLW
   647  	ASLWCC
   648  	ASRW
   649  	ASRAW
   650  	ASRAWCC
   651  	ASRWCC
   652  	ASTBCCC
   653  	ASTHCCC
   654  	ASTSW
   655  	ASTWCCC
   656  	ASUB
   657  	ASUBCC
   658  	ASUBVCC
   659  	ASUBC
   660  	ASUBCCC
   661  	ASUBCV
   662  	ASUBCVCC
   663  	ASUBME
   664  	ASUBMECC
   665  	ASUBMEVCC
   666  	ASUBMEV
   667  	ASUBV
   668  	ASUBE
   669  	ASUBECC
   670  	ASUBEV
   671  	ASUBEVCC
   672  	ASUBZE
   673  	ASUBZECC
   674  	ASUBZEVCC
   675  	ASUBZEV
   676  	ASYNC
   677  	AXOR
   678  	AXORCC
   679  	AXORIS
   680  
   681  	ADCBF
   682  	ADCBI
   683  	ADCBST
   684  	ADCBT
   685  	ADCBTST
   686  	ADCBZ
   687  	AEIEIO
   688  	AICBI
   689  	AISYNC
   690  	APTESYNC
   691  	ATLBIE
   692  	ATLBIEL
   693  	ATLBSYNC
   694  	ATW
   695  
   696  	ASYSCALL
   697  	AWORD
   698  
   699  	ARFCI
   700  
   701  	AFCPSGN
   702  	AFCPSGNCC
   703  	/* optional on 32-bit */
   704  	AFRES
   705  	AFRESCC
   706  	AFRIM
   707  	AFRIMCC
   708  	AFRIP
   709  	AFRIPCC
   710  	AFRIZ
   711  	AFRIZCC
   712  	AFRIN
   713  	AFRINCC
   714  	AFRSQRTE
   715  	AFRSQRTECC
   716  	AFSEL
   717  	AFSELCC
   718  	AFSQRT
   719  	AFSQRTCC
   720  	AFSQRTS
   721  	AFSQRTSCC
   722  
   723  	/* 64-bit */
   724  
   725  	ACNTLZD
   726  	ACNTLZDCC
   727  	ACMPW /* CMP with L=0 */
   728  	ACMPWU
   729  	ACMPB
   730  	AFTDIV
   731  	AFTSQRT
   732  	ADIVD
   733  	ADIVDCC
   734  	ADIVDE
   735  	ADIVDECC
   736  	ADIVDEU
   737  	ADIVDEUCC
   738  	ADIVDVCC
   739  	ADIVDV
   740  	ADIVDU
   741  	ADIVDUCC
   742  	ADIVDUVCC
   743  	ADIVDUV
   744  	AEXTSW
   745  	AEXTSWCC
   746  	/* AFCFIW; AFCFIWCC */
   747  	AFCFID
   748  	AFCFIDCC
   749  	AFCFIDU
   750  	AFCFIDUCC
   751  	AFCFIDS
   752  	AFCFIDSCC
   753  	AFCTID
   754  	AFCTIDCC
   755  	AFCTIDZ
   756  	AFCTIDZCC
   757  	ALDAR
   758  	AMOVD
   759  	AMOVDU
   760  	AMOVWZ
   761  	AMOVWZU
   762  	AMULHD
   763  	AMULHDCC
   764  	AMULHDU
   765  	AMULHDUCC
   766  	AMULLD
   767  	AMULLDCC
   768  	AMULLDVCC
   769  	AMULLDV
   770  	ARFID
   771  	ARLDMI
   772  	ARLDMICC
   773  	ARLDIMI
   774  	ARLDIMICC
   775  	ARLDC
   776  	ARLDCCC
   777  	ARLDCR
   778  	ARLDCRCC
   779  	ARLDICR
   780  	ARLDICRCC
   781  	ARLDCL
   782  	ARLDCLCC
   783  	ARLDICL
   784  	ARLDICLCC
   785  	ARLDIC
   786  	ARLDICCC
   787  	ACLRLSLDI
   788  	AROTL
   789  	AROTLW
   790  	ASLBIA
   791  	ASLBIE
   792  	ASLBMFEE
   793  	ASLBMFEV
   794  	ASLBMTE
   795  	ASLD
   796  	ASLDCC
   797  	ASRD
   798  	ASRAD
   799  	ASRADCC
   800  	ASRDCC
   801  	AEXTSWSLI
   802  	AEXTSWSLICC
   803  	ASTDCCC
   804  	ATD
   805  	ASETB
   806  
   807  	/* 64-bit pseudo operation */
   808  	ADWORD
   809  	AREMD
   810  	AREMDU
   811  
   812  	/* more 64-bit operations */
   813  	AHRFID
   814  	APOPCNTD
   815  	APOPCNTW
   816  	APOPCNTB
   817  	ACNTTZW
   818  	ACNTTZWCC
   819  	ACNTTZD
   820  	ACNTTZDCC
   821  	ACOPY
   822  	APASTECC
   823  	ADARN
   824  	AMADDHD
   825  	AMADDHDU
   826  	AMADDLD
   827  
   828  	/* Vector */
   829  	ALVEBX
   830  	ALVEHX
   831  	ALVEWX
   832  	ALVX
   833  	ALVXL
   834  	ALVSL
   835  	ALVSR
   836  	ASTVEBX
   837  	ASTVEHX
   838  	ASTVEWX
   839  	ASTVX
   840  	ASTVXL
   841  	AVAND
   842  	AVANDC
   843  	AVNAND
   844  	AVOR
   845  	AVORC
   846  	AVNOR
   847  	AVXOR
   848  	AVEQV
   849  	AVADDUM
   850  	AVADDUBM
   851  	AVADDUHM
   852  	AVADDUWM
   853  	AVADDUDM
   854  	AVADDUQM
   855  	AVADDCU
   856  	AVADDCUQ
   857  	AVADDCUW
   858  	AVADDUS
   859  	AVADDUBS
   860  	AVADDUHS
   861  	AVADDUWS
   862  	AVADDSS
   863  	AVADDSBS
   864  	AVADDSHS
   865  	AVADDSWS
   866  	AVADDE
   867  	AVADDEUQM
   868  	AVADDECUQ
   869  	AVSUBUM
   870  	AVSUBUBM
   871  	AVSUBUHM
   872  	AVSUBUWM
   873  	AVSUBUDM
   874  	AVSUBUQM
   875  	AVSUBCU
   876  	AVSUBCUQ
   877  	AVSUBCUW
   878  	AVSUBUS
   879  	AVSUBUBS
   880  	AVSUBUHS
   881  	AVSUBUWS
   882  	AVSUBSS
   883  	AVSUBSBS
   884  	AVSUBSHS
   885  	AVSUBSWS
   886  	AVSUBE
   887  	AVSUBEUQM
   888  	AVSUBECUQ
   889  	AVMULESB
   890  	AVMULOSB
   891  	AVMULEUB
   892  	AVMULOUB
   893  	AVMULESH
   894  	AVMULOSH
   895  	AVMULEUH
   896  	AVMULOUH
   897  	AVMULESW
   898  	AVMULOSW
   899  	AVMULEUW
   900  	AVMULOUW
   901  	AVMULUWM
   902  	AVPMSUM
   903  	AVPMSUMB
   904  	AVPMSUMH
   905  	AVPMSUMW
   906  	AVPMSUMD
   907  	AVMSUMUDM
   908  	AVR
   909  	AVRLB
   910  	AVRLH
   911  	AVRLW
   912  	AVRLD
   913  	AVS
   914  	AVSLB
   915  	AVSLH
   916  	AVSLW
   917  	AVSL
   918  	AVSLO
   919  	AVSRB
   920  	AVSRH
   921  	AVSRW
   922  	AVSR
   923  	AVSRO
   924  	AVSLD
   925  	AVSRD
   926  	AVSA
   927  	AVSRAB
   928  	AVSRAH
   929  	AVSRAW
   930  	AVSRAD
   931  	AVSOI
   932  	AVSLDOI
   933  	AVCLZ
   934  	AVCLZB
   935  	AVCLZH
   936  	AVCLZW
   937  	AVCLZD
   938  	AVPOPCNT
   939  	AVPOPCNTB
   940  	AVPOPCNTH
   941  	AVPOPCNTW
   942  	AVPOPCNTD
   943  	AVCMPEQ
   944  	AVCMPEQUB
   945  	AVCMPEQUBCC
   946  	AVCMPEQUH
   947  	AVCMPEQUHCC
   948  	AVCMPEQUW
   949  	AVCMPEQUWCC
   950  	AVCMPEQUD
   951  	AVCMPEQUDCC
   952  	AVCMPGT
   953  	AVCMPGTUB
   954  	AVCMPGTUBCC
   955  	AVCMPGTUH
   956  	AVCMPGTUHCC
   957  	AVCMPGTUW
   958  	AVCMPGTUWCC
   959  	AVCMPGTUD
   960  	AVCMPGTUDCC
   961  	AVCMPGTSB
   962  	AVCMPGTSBCC
   963  	AVCMPGTSH
   964  	AVCMPGTSHCC
   965  	AVCMPGTSW
   966  	AVCMPGTSWCC
   967  	AVCMPGTSD
   968  	AVCMPGTSDCC
   969  	AVCMPNEZB
   970  	AVCMPNEZBCC
   971  	AVCMPNEB
   972  	AVCMPNEBCC
   973  	AVCMPNEH
   974  	AVCMPNEHCC
   975  	AVCMPNEW
   976  	AVCMPNEWCC
   977  	AVPERM
   978  	AVPERMXOR
   979  	AVPERMR
   980  	AVBPERMQ
   981  	AVBPERMD
   982  	AVSEL
   983  	AVSPLTB
   984  	AVSPLTH
   985  	AVSPLTW
   986  	AVSPLTISB
   987  	AVSPLTISH
   988  	AVSPLTISW
   989  	AVCIPH
   990  	AVCIPHER
   991  	AVCIPHERLAST
   992  	AVNCIPH
   993  	AVNCIPHER
   994  	AVNCIPHERLAST
   995  	AVSBOX
   996  	AVSHASIGMA
   997  	AVSHASIGMAW
   998  	AVSHASIGMAD
   999  	AVMRGEW
  1000  	AVMRGOW
  1001  	AVCLZLSBB
  1002  	AVCTZLSBB
  1003  
  1004  	/* VSX */
  1005  	ALXV
  1006  	ALXVL
  1007  	ALXVLL
  1008  	ALXVD2X
  1009  	ALXVW4X
  1010  	ALXVH8X
  1011  	ALXVB16X
  1012  	ALXVX
  1013  	ALXVDSX
  1014  	ASTXV
  1015  	ASTXVL
  1016  	ASTXVLL
  1017  	ASTXVD2X
  1018  	ASTXVW4X
  1019  	ASTXVH8X
  1020  	ASTXVB16X
  1021  	ASTXVX
  1022  	ALXSDX
  1023  	ASTXSDX
  1024  	ALXSIWAX
  1025  	ALXSIWZX
  1026  	ASTXSIWX
  1027  	AMFVSRD
  1028  	AMFFPRD
  1029  	AMFVRD
  1030  	AMFVSRWZ
  1031  	AMFVSRLD
  1032  	AMTVSRD
  1033  	AMTFPRD
  1034  	AMTVRD
  1035  	AMTVSRWA
  1036  	AMTVSRWZ
  1037  	AMTVSRDD
  1038  	AMTVSRWS
  1039  	AXXLAND
  1040  	AXXLANDC
  1041  	AXXLEQV
  1042  	AXXLNAND
  1043  	AXXLOR
  1044  	AXXLORC
  1045  	AXXLNOR
  1046  	AXXLORQ
  1047  	AXXLXOR
  1048  	AXXSEL
  1049  	AXXMRGHW
  1050  	AXXMRGLW
  1051  	AXXSPLTW
  1052  	AXXSPLTIB
  1053  	AXXPERM
  1054  	AXXPERMDI
  1055  	AXXSLDWI
  1056  	AXXBRQ
  1057  	AXXBRD
  1058  	AXXBRW
  1059  	AXXBRH
  1060  	AXSCVDPSP
  1061  	AXSCVSPDP
  1062  	AXSCVDPSPN
  1063  	AXSCVSPDPN
  1064  	AXVCVDPSP
  1065  	AXVCVSPDP
  1066  	AXSCVDPSXDS
  1067  	AXSCVDPSXWS
  1068  	AXSCVDPUXDS
  1069  	AXSCVDPUXWS
  1070  	AXSCVSXDDP
  1071  	AXSCVUXDDP
  1072  	AXSCVSXDSP
  1073  	AXSCVUXDSP
  1074  	AXVCVDPSXDS
  1075  	AXVCVDPSXWS
  1076  	AXVCVDPUXDS
  1077  	AXVCVDPUXWS
  1078  	AXVCVSPSXDS
  1079  	AXVCVSPSXWS
  1080  	AXVCVSPUXDS
  1081  	AXVCVSPUXWS
  1082  	AXVCVSXDDP
  1083  	AXVCVSXWDP
  1084  	AXVCVUXDDP
  1085  	AXVCVUXWDP
  1086  	AXVCVSXDSP
  1087  	AXVCVSXWSP
  1088  	AXVCVUXDSP
  1089  	AXVCVUXWSP
  1090  	AXSMAXJDP
  1091  	AXSMINJDP
  1092  	ALASTAOUT // The last instruction in this list. Also the first opcode generated by ppc64map.
  1093  
  1094  	// aliases
  1095  	ABR   = obj.AJMP
  1096  	ABL   = obj.ACALL
  1097  	ALAST = ALASTGEN // The final enumerated instruction value + 1. This is used to size the oprange table.
  1098  )
  1099
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