1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 // GOPPC64 values indicate power8, power9, etc.
6 // That means the code is compiled for that target,
7 // and will not run on earlier targets.
8 //
9 (Add(Ptr|64|32|16|8) ...) => (ADD ...)
10 (Add64F ...) => (FADD ...)
11 (Add32F ...) => (FADDS ...)
12
13 (Sub(Ptr|64|32|16|8) ...) => (SUB ...)
14 (Sub32F ...) => (FSUBS ...)
15 (Sub64F ...) => (FSUB ...)
16
17 (Min(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMINJDP x y)
18 (Max(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMAXJDP x y)
19
20 // Combine 64 bit integer multiply and adds
21 (ADD l:(MULLD x y) z) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD x y z)
22
23 (Mod16 x y) => (Mod32 (SignExt16to32 x) (SignExt16to32 y))
24 (Mod16u x y) => (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y))
25 (Mod8 x y) => (Mod32 (SignExt8to32 x) (SignExt8to32 y))
26 (Mod8u x y) => (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y))
27 (Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y)
28 (Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y)))
29 (Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y)
30 (Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y)))
31 (Mod32 x y) && buildcfg.GOPPC64 >= 9 => (MODSW x y)
32 (Mod32 x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVW x y)))
33 (Mod32u x y) && buildcfg.GOPPC64 >= 9 => (MODUW x y)
34 (Mod32u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVWU x y)))
35
36 // (x + y) / 2 with x>=y => (x - y) / 2 + y
37 (Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
38
39 (Mul64 ...) => (MULLD ...)
40 (Mul(32|16|8) ...) => (MULLW ...)
41 (Select0 (Mul64uhilo x y)) => (MULHDU x y)
42 (Select1 (Mul64uhilo x y)) => (MULLD x y)
43
44 (Div64 [false] x y) => (DIVD x y)
45 (Div64u ...) => (DIVDU ...)
46 (Div32 [false] x y) => (DIVW x y)
47 (Div32u ...) => (DIVWU ...)
48 (Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y))
49 (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
50 (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y))
51 (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))
52
53 (Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)
54
55 (Mul(32|64)F ...) => ((FMULS|FMUL) ...)
56
57 (Div(32|64)F ...) => ((FDIVS|FDIV) ...)
58
59 // Lowering float <=> int
60 (Cvt32to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD (SignExt32to64 x)))
61 (Cvt64to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD x))
62
63 (Cvt32Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x))
64 (Cvt64Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x))
65
66 (Cvt32Fto64F ...) => (Copy ...) // Note v will have the wrong type for patterns dependent on Float32/Float64
67 (Cvt64Fto32F ...) => (FRSP ...)
68
69 (CvtBoolToUint8 ...) => (Copy ...)
70
71 (Round(32|64)F ...) => (LoweredRound(32|64)F ...)
72
73 (Sqrt ...) => (FSQRT ...)
74 (Sqrt32 ...) => (FSQRTS ...)
75 (Floor ...) => (FFLOOR ...)
76 (Ceil ...) => (FCEIL ...)
77 (Trunc ...) => (FTRUNC ...)
78 (Round ...) => (FROUND ...)
79 (Copysign x y) => (FCPSGN y x)
80 (Abs ...) => (FABS ...)
81 (FMA ...) => (FMADD ...)
82
83 // Lowering extension
84 // Note: we always extend to 64 bits even though some ops don't need that many result bits.
85 (SignExt8to(16|32|64) ...) => (MOVBreg ...)
86 (SignExt16to(32|64) ...) => (MOVHreg ...)
87 (SignExt32to64 ...) => (MOVWreg ...)
88
89 (ZeroExt8to(16|32|64) ...) => (MOVBZreg ...)
90 (ZeroExt16to(32|64) ...) => (MOVHZreg ...)
91 (ZeroExt32to64 ...) => (MOVWZreg ...)
92
93 (Trunc(16|32|64)to8 <t> x) && t.IsSigned() => (MOVBreg x)
94 (Trunc(16|32|64)to8 x) => (MOVBZreg x)
95 (Trunc(32|64)to16 <t> x) && t.IsSigned() => (MOVHreg x)
96 (Trunc(32|64)to16 x) => (MOVHZreg x)
97 (Trunc64to32 <t> x) && t.IsSigned() => (MOVWreg x)
98 (Trunc64to32 x) => (MOVWZreg x)
99
100 // Lowering constants
101 (Const(64|32|16|8) [val]) => (MOVDconst [int64(val)])
102 (Const(32|64)F ...) => (FMOV(S|D)const ...)
103 (ConstNil) => (MOVDconst [0])
104 (ConstBool [t]) => (MOVDconst [b2i(t)])
105
106 // Carrying addition.
107 (Select0 (Add64carry x y c)) => (Select0 <typ.UInt64> (ADDE x y (Select1 <typ.UInt64> (ADDCconst c [-1]))))
108 (Select1 (Add64carry x y c)) => (ADDZEzero (Select1 <typ.UInt64> (ADDE x y (Select1 <typ.UInt64> (ADDCconst c [-1])))))
109 // Fold initial carry bit if 0.
110 (ADDE x y (Select1 <typ.UInt64> (ADDCconst (MOVDconst [0]) [-1]))) => (ADDC x y)
111 // Fold transfer of CA -> GPR -> CA. Note 2 uses when feeding into a chained Add64carry.
112 (Select1 (ADDCconst n:(ADDZEzero x) [-1])) && n.Uses <= 2 => x
113 (ADDE (MOVDconst [0]) y c) => (ADDZE y c)
114
115 // Borrowing subtraction.
116 (Select0 (Sub64borrow x y c)) => (Select0 <typ.UInt64> (SUBE x y (Select1 <typ.UInt64> (SUBCconst c [0]))))
117 (Select1 (Sub64borrow x y c)) => (NEG (SUBZEzero (Select1 <typ.UInt64> (SUBE x y (Select1 <typ.UInt64> (SUBCconst c [0]))))))
118 // Fold initial borrow bit if 0.
119 (SUBE x y (Select1 <typ.UInt64> (SUBCconst (MOVDconst [0]) [0]))) => (SUBC x y)
120 // Fold transfer of CA -> GPR -> CA. Note 2 uses when feeding into a chained Sub64borrow.
121 (Select1 (SUBCconst n:(NEG (SUBZEzero x)) [0])) && n.Uses <= 2 => x
122
123 // Constant folding
124 (FABS (FMOVDconst [x])) => (FMOVDconst [math.Abs(x)])
125 (FSQRT (FMOVDconst [x])) && x >= 0 => (FMOVDconst [math.Sqrt(x)])
126 (FFLOOR (FMOVDconst [x])) => (FMOVDconst [math.Floor(x)])
127 (FCEIL (FMOVDconst [x])) => (FMOVDconst [math.Ceil(x)])
128 (FTRUNC (FMOVDconst [x])) => (FMOVDconst [math.Trunc(x)])
129
130 // Rotates
131 (RotateLeft8 <t> x (MOVDconst [c])) => (Or8 (Lsh8x64 <t> x (MOVDconst [c&7])) (Rsh8Ux64 <t> x (MOVDconst [-c&7])))
132 (RotateLeft16 <t> x (MOVDconst [c])) => (Or16 (Lsh16x64 <t> x (MOVDconst [c&15])) (Rsh16Ux64 <t> x (MOVDconst [-c&15])))
133 (RotateLeft(32|64) ...) => ((ROTLW|ROTL) ...)
134
135 // Constant rotate generation
136 (ROTLW x (MOVDconst [c])) => (ROTLWconst x [c&31])
137 (ROTL x (MOVDconst [c])) => (ROTLconst x [c&63])
138
139 // Combine rotate and mask operations
140 (ANDconst [m] (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x)
141 (AND (MOVDconst [m]) (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x)
142 (ANDconst [m] (ROTLW x r)) && isPPC64WordRotateMask(m) => (RLWNM [encodePPC64RotateMask(0,m,32)] x r)
143 (AND (MOVDconst [m]) (ROTLW x r)) && isPPC64WordRotateMask(m) => (RLWNM [encodePPC64RotateMask(0,m,32)] x r)
144
145 // Note, any rotated word bitmask is still a valid word bitmask.
146 (ROTLWconst [r] (AND (MOVDconst [m]) x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,rotateLeft32(m,r),32)] x)
147 (ROTLWconst [r] (ANDconst [m] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,rotateLeft32(m,r),32)] x)
148
149 (ANDconst [m] (SRWconst x [s])) && mergePPC64RShiftMask(m,s,32) == 0 => (MOVDconst [0])
150 (ANDconst [m] (SRWconst x [s])) && mergePPC64AndSrwi(m,s) != 0 => (RLWINM [mergePPC64AndSrwi(m,s)] x)
151 (AND (MOVDconst [m]) (SRWconst x [s])) && mergePPC64RShiftMask(m,s,32) == 0 => (MOVDconst [0])
152 (AND (MOVDconst [m]) (SRWconst x [s])) && mergePPC64AndSrwi(m,s) != 0 => (RLWINM [mergePPC64AndSrwi(m,s)] x)
153
154 (SRWconst (ANDconst [m] x) [s]) && mergePPC64RShiftMask(m>>uint(s),s,32) == 0 => (MOVDconst [0])
155 (SRWconst (ANDconst [m] x) [s]) && mergePPC64AndSrwi(m>>uint(s),s) != 0 => (RLWINM [mergePPC64AndSrwi(m>>uint(s),s)] x)
156 (SRWconst (AND (MOVDconst [m]) x) [s]) && mergePPC64RShiftMask(m>>uint(s),s,32) == 0 => (MOVDconst [0])
157 (SRWconst (AND (MOVDconst [m]) x) [s]) && mergePPC64AndSrwi(m>>uint(s),s) != 0 => (RLWINM [mergePPC64AndSrwi(m>>uint(s),s)] x)
158
159 // Merge shift right + shift left and clear left (e.g for a table lookup)
160 (CLRLSLDI [c] (SRWconst [s] x)) && mergePPC64ClrlsldiSrw(int64(c),s) != 0 => (RLWINM [mergePPC64ClrlsldiSrw(int64(c),s)] x)
161 (CLRLSLDI [c] (SRDconst [s] x)) && mergePPC64ClrlsldiSrd(int64(c),s) != 0 => (RLWINM [mergePPC64ClrlsldiSrd(int64(c),s)] x)
162 (SLDconst [l] (SRWconst [r] x)) && mergePPC64SldiSrw(l,r) != 0 => (RLWINM [mergePPC64SldiSrw(l,r)] x)
163 // The following reduction shows up frequently too. e.g b[(x>>14)&0xFF]
164 (CLRLSLDI [c] i:(RLWINM [s] x)) && mergePPC64ClrlsldiRlwinm(c,s) != 0 => (RLWINM [mergePPC64ClrlsldiRlwinm(c,s)] x)
165
166 // large constant signed right shift, we leave the sign bit
167 (Rsh64x64 x (MOVDconst [c])) && uint64(c) >= 64 => (SRADconst x [63])
168 (Rsh32x64 x (MOVDconst [c])) && uint64(c) >= 32 => (SRAWconst x [63])
169 (Rsh16x64 x (MOVDconst [c])) && uint64(c) >= 16 => (SRAWconst (SignExt16to32 x) [63])
170 (Rsh8x64 x (MOVDconst [c])) && uint64(c) >= 8 => (SRAWconst (SignExt8to32 x) [63])
171
172 // constant shifts
173 ((Lsh64|Rsh64|Rsh64U)x64 x (MOVDconst [c])) && uint64(c) < 64 => (S(L|RA|R)Dconst x [c])
174 ((Lsh32|Rsh32|Rsh32U)x64 x (MOVDconst [c])) && uint64(c) < 32 => (S(L|RA|R)Wconst x [c])
175 ((Rsh16|Rsh16U)x64 x (MOVDconst [c])) && uint64(c) < 16 => (SR(AW|W)const ((Sign|Zero)Ext16to32 x) [c])
176 (Lsh16x64 x (MOVDconst [c])) && uint64(c) < 16 => (SLWconst x [c])
177 ((Rsh8|Rsh8U)x64 x (MOVDconst [c])) && uint64(c) < 8 => (SR(AW|W)const ((Sign|Zero)Ext8to32 x) [c])
178 (Lsh8x64 x (MOVDconst [c])) && uint64(c) < 8 => (SLWconst x [c])
179
180 // Lower bounded shifts first. No need to check shift value.
181 (Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
182 (Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y)
183 (Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
184 (Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
185 (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
186 (Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)
187 (Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVHZreg x) y)
188 (Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVBZreg x) y)
189 (Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD x y)
190 (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y)
191 (Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVHreg x) y)
192 (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVBreg x) y)
193
194 // Unbounded shifts. Go shifts saturate to 0 or -1 when shifting beyond the number of
195 // bits in a type, PPC64 shifts do not (see the ISA for details).
196 //
197 // Note, y is always non-negative.
198 //
199 // Note, ISELZ is intentionally not used in lower. Where possible, ISEL is converted to ISELZ in late lower
200 // after all the ISEL folding rules have been exercised.
201
202 ((Rsh64U|Lsh64)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPUconst y [64]))
203 ((Rsh64U|Lsh64)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPWUconst y [64]))
204 ((Rsh64U|Lsh64)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFC0] y)))
205 ((Rsh64U|Lsh64)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0x00C0] y)))
206 (Rsh64x(64|32) <t> x y) => (ISEL [0] (SRAD <t> x y) (SRADconst <t> x [63]) (CMP(U|WU)const y [64]))
207 (Rsh64x16 <t> x y) => (ISEL [2] (SRAD <t> x y) (SRADconst <t> x [63]) (CMPconst [0] (ANDconst [0xFFC0] y)))
208 (Rsh64x8 <t> x y) => (ISEL [2] (SRAD <t> x y) (SRADconst <t> x [63]) (CMPconst [0] (ANDconst [0x00C0] y)))
209
210 ((Rsh32U|Lsh32)x64 <t> x y) => (ISEL [0] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPUconst y [32]))
211 ((Rsh32U|Lsh32)x32 <t> x y) => (ISEL [0] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPWUconst y [32]))
212 ((Rsh32U|Lsh32)x16 <t> x y) => (ISEL [2] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFE0] y)))
213 ((Rsh32U|Lsh32)x8 <t> x y) => (ISEL [2] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0x00E0] y)))
214 (Rsh32x(64|32) <t> x y) => (ISEL [0] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMP(U|WU)const y [32]))
215 (Rsh32x16 <t> x y) => (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (ANDconst [0xFFE0] y)))
216 (Rsh32x8 <t> x y) => (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (ANDconst [0x00E0] y)))
217
218 ((Rsh16U|Lsh16)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPUconst y [16]))
219 ((Rsh16U|Lsh16)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPWUconst y [16]))
220 ((Rsh16U|Lsh16)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFF0] y)))
221 ((Rsh16U|Lsh16)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0x00F0] y)))
222 (Rsh16x(64|32) <t> x y) => (ISEL [0] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (CMP(U|WU)const y [16]))
223 (Rsh16x16 <t> x y) => (ISEL [2] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (CMPconst [0] (ANDconst [0xFFF0] y)))
224 (Rsh16x8 <t> x y) => (ISEL [2] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (CMPconst [0] (ANDconst [0x00F0] y)))
225
226 ((Rsh8U|Lsh8)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPUconst y [8]))
227 ((Rsh8U|Lsh8)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPWUconst y [8]))
228 ((Rsh8U|Lsh8)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFF8] y)))
229 ((Rsh8U|Lsh8)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0x00F8] y)))
230 (Rsh8x(64|32) <t> x y) => (ISEL [0] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (CMP(U|WU)const y [8]))
231 (Rsh8x16 <t> x y) => (ISEL [2] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (CMPconst [0] (ANDconst [0xFFF8] y)))
232 (Rsh8x8 <t> x y) => (ISEL [2] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (CMPconst [0] (ANDconst [0x00F8] y)))
233
234 // Catch bounded shifts in situations like foo<<uint(shift&63) which might not be caught by the prove pass.
235 (CMP(U|WU)const [d] (ANDconst z [c])) && uint64(d) > uint64(c) => (FlagLT)
236
237 (ORN x (MOVDconst [-1])) => x
238
239 (S(RAD|RD|LD) x (MOVDconst [c])) => (S(RAD|RD|LD)const [c&63 | (c>>6&1*63)] x)
240 (S(RAW|RW|LW) x (MOVDconst [c])) => (S(RAW|RW|LW)const [c&31 | (c>>5&1*31)] x)
241
242 (Addr {sym} base) => (MOVDaddr {sym} [0] base)
243 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVDaddr {sym} (SPanchored base mem))
244 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVDaddr {sym} base)
245 (OffPtr [off] ptr) => (ADD (MOVDconst <typ.Int64> [off]) ptr)
246 (MOVDaddr {sym} [n] p:(ADD x y)) && sym == nil && n == 0 => p
247 (MOVDaddr {sym} [n] ptr) && sym == nil && n == 0 && (ptr.Op == OpArgIntReg || ptr.Op == OpPhi) => ptr
248
249 // TODO: optimize these cases?
250 (Ctz32NonZero ...) => (Ctz32 ...)
251 (Ctz64NonZero ...) => (Ctz64 ...)
252
253 (Ctz64 x) && buildcfg.GOPPC64<=8 => (POPCNTD (ANDN <typ.Int64> (ADDconst <typ.Int64> [-1] x) x))
254 (Ctz64 x) => (CNTTZD x)
255 (Ctz32 x) && buildcfg.GOPPC64<=8 => (POPCNTW (MOVWZreg (ANDN <typ.Int> (ADDconst <typ.Int> [-1] x) x)))
256 (Ctz32 x) => (CNTTZW (MOVWZreg x))
257 (Ctz16 x) => (POPCNTW (MOVHZreg (ANDN <typ.Int16> (ADDconst <typ.Int16> [-1] x) x)))
258 (Ctz8 x) => (POPCNTB (MOVBZreg (ANDN <typ.UInt8> (ADDconst <typ.UInt8> [-1] x) x)))
259
260 (BitLen64 x) => (SUBFCconst [64] (CNTLZD <typ.Int> x))
261 (BitLen32 x) => (SUBFCconst [32] (CNTLZW <typ.Int> x))
262
263 (PopCount64 ...) => (POPCNTD ...)
264 (PopCount(32|16|8) x) => (POPCNT(W|W|B) (MOV(W|H|B)Zreg x))
265
266 (And(64|32|16|8) ...) => (AND ...)
267 (Or(64|32|16|8) ...) => (OR ...)
268 (Xor(64|32|16|8) ...) => (XOR ...)
269
270 (Neg(64|32|16|8) ...) => (NEG ...)
271 (Neg(64|32)F ...) => (FNEG ...)
272
273 (Com(64|32|16|8) x) => (NOR x x)
274
275 // Lowering boolean ops
276 (AndB ...) => (AND ...)
277 (OrB ...) => (OR ...)
278 (Not x) => (XORconst [1] x)
279
280 // Merge logical operations
281 (AND x (NOR y y)) => (ANDN x y)
282 (OR x (NOR y y)) => (ORN x y)
283
284 // Lowering comparisons
285 (EqB x y) => (ANDconst [1] (EQV x y))
286 // Sign extension dependence on operand sign sets up for sign/zero-extension elision later
287 (Eq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (Equal (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
288 (Eq(8|16) x y) => (Equal (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
289 (Eq(32|64|Ptr) x y) => (Equal ((CMPW|CMP|CMP) x y))
290 (Eq(32|64)F x y) => (Equal (FCMPU x y))
291
292 (NeqB ...) => (XOR ...)
293 // Like Eq8 and Eq16, prefer sign extension likely to enable later elision.
294 (Neq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (NotEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
295 (Neq(8|16) x y) => (NotEqual (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
296 (Neq(32|64|Ptr) x y) => (NotEqual ((CMPW|CMP|CMP) x y))
297 (Neq(32|64)F x y) => (NotEqual (FCMPU x y))
298
299 (Less(8|16) x y) => (LessThan (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
300 (Less(32|64) x y) => (LessThan ((CMPW|CMP) x y))
301 (Less(32|64)F x y) => (FLessThan (FCMPU x y))
302
303 (Less(8|16)U x y) => (LessThan (CMPWU (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
304 (Less(32|64)U x y) => (LessThan ((CMPWU|CMPU) x y))
305
306 (Leq(8|16) x y) => (LessEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
307 (Leq(32|64) x y) => (LessEqual ((CMPW|CMP) x y))
308 (Leq(32|64)F x y) => (FLessEqual (FCMPU x y))
309
310 (Leq(8|16)U x y) => (LessEqual (CMPWU (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
311 (Leq(32|64)U x y) => (LessEqual (CMP(WU|U) x y))
312
313 // Absorb pseudo-ops into blocks.
314 (If (Equal cc) yes no) => (EQ cc yes no)
315 (If (NotEqual cc) yes no) => (NE cc yes no)
316 (If (LessThan cc) yes no) => (LT cc yes no)
317 (If (LessEqual cc) yes no) => (LE cc yes no)
318 (If (GreaterThan cc) yes no) => (GT cc yes no)
319 (If (GreaterEqual cc) yes no) => (GE cc yes no)
320 (If (FLessThan cc) yes no) => (FLT cc yes no)
321 (If (FLessEqual cc) yes no) => (FLE cc yes no)
322 (If (FGreaterThan cc) yes no) => (FGT cc yes no)
323 (If (FGreaterEqual cc) yes no) => (FGE cc yes no)
324
325 (If cond yes no) => (NE (CMPconst [0] (ANDconst [1] cond)) yes no)
326
327 // Absorb boolean tests into block
328 (NE (CMPconst [0] (ANDconst [1] ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) cc))) yes no) => ((EQ|NE|LT|LE|GT|GE) cc yes no)
329 (NE (CMPconst [0] (ANDconst [1] ((FLessThan|FLessEqual|FGreaterThan|FGreaterEqual) cc))) yes no) => ((FLT|FLE|FGT|FGE) cc yes no)
330
331 // absorb flag constants into branches
332 (EQ (FlagEQ) yes no) => (First yes no)
333 (EQ (FlagLT) yes no) => (First no yes)
334 (EQ (FlagGT) yes no) => (First no yes)
335
336 (NE (FlagEQ) yes no) => (First no yes)
337 (NE (FlagLT) yes no) => (First yes no)
338 (NE (FlagGT) yes no) => (First yes no)
339
340 (LT (FlagEQ) yes no) => (First no yes)
341 (LT (FlagLT) yes no) => (First yes no)
342 (LT (FlagGT) yes no) => (First no yes)
343
344 (LE (FlagEQ) yes no) => (First yes no)
345 (LE (FlagLT) yes no) => (First yes no)
346 (LE (FlagGT) yes no) => (First no yes)
347
348 (GT (FlagEQ) yes no) => (First no yes)
349 (GT (FlagLT) yes no) => (First no yes)
350 (GT (FlagGT) yes no) => (First yes no)
351
352 (GE (FlagEQ) yes no) => (First yes no)
353 (GE (FlagLT) yes no) => (First no yes)
354 (GE (FlagGT) yes no) => (First yes no)
355
356 // absorb InvertFlags into branches
357 (LT (InvertFlags cmp) yes no) => (GT cmp yes no)
358 (GT (InvertFlags cmp) yes no) => (LT cmp yes no)
359 (LE (InvertFlags cmp) yes no) => (GE cmp yes no)
360 (GE (InvertFlags cmp) yes no) => (LE cmp yes no)
361 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
362 (NE (InvertFlags cmp) yes no) => (NE cmp yes no)
363
364 // constant comparisons
365 (CMPWconst (MOVDconst [x]) [y]) && int32(x)==int32(y) => (FlagEQ)
366 (CMPWconst (MOVDconst [x]) [y]) && int32(x)<int32(y) => (FlagLT)
367 (CMPWconst (MOVDconst [x]) [y]) && int32(x)>int32(y) => (FlagGT)
368
369 (CMPconst (MOVDconst [x]) [y]) && x==y => (FlagEQ)
370 (CMPconst (MOVDconst [x]) [y]) && x<y => (FlagLT)
371 (CMPconst (MOVDconst [x]) [y]) && x>y => (FlagGT)
372
373 (CMPWUconst (MOVDconst [x]) [y]) && int32(x)==int32(y) => (FlagEQ)
374 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)<uint32(y) => (FlagLT)
375 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)>uint32(y) => (FlagGT)
376
377 (CMPUconst (MOVDconst [x]) [y]) && x==y => (FlagEQ)
378 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)<uint64(y) => (FlagLT)
379 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)>uint64(y) => (FlagGT)
380
381 // absorb flag constants into boolean values
382 (Equal (FlagEQ)) => (MOVDconst [1])
383 (Equal (FlagLT)) => (MOVDconst [0])
384 (Equal (FlagGT)) => (MOVDconst [0])
385
386 (NotEqual (FlagEQ)) => (MOVDconst [0])
387 (NotEqual (FlagLT)) => (MOVDconst [1])
388 (NotEqual (FlagGT)) => (MOVDconst [1])
389
390 (LessThan (FlagEQ)) => (MOVDconst [0])
391 (LessThan (FlagLT)) => (MOVDconst [1])
392 (LessThan (FlagGT)) => (MOVDconst [0])
393
394 (LessEqual (FlagEQ)) => (MOVDconst [1])
395 (LessEqual (FlagLT)) => (MOVDconst [1])
396 (LessEqual (FlagGT)) => (MOVDconst [0])
397
398 (GreaterThan (FlagEQ)) => (MOVDconst [0])
399 (GreaterThan (FlagLT)) => (MOVDconst [0])
400 (GreaterThan (FlagGT)) => (MOVDconst [1])
401
402 (GreaterEqual (FlagEQ)) => (MOVDconst [1])
403 (GreaterEqual (FlagLT)) => (MOVDconst [0])
404 (GreaterEqual (FlagGT)) => (MOVDconst [1])
405
406 // absorb InvertFlags into boolean values
407 ((Equal|NotEqual|LessThan|GreaterThan|LessEqual|GreaterEqual) (InvertFlags x)) => ((Equal|NotEqual|GreaterThan|LessThan|GreaterEqual|LessEqual) x)
408
409
410 // Elide compares of bit tests
411 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (ANDCC x y)) yes no)
412 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(OR x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (ORCC x y)) yes no)
413 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(XOR x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (XORCC x y)) yes no)
414
415 (CondSelect x y (SETBC [a] cmp)) => (ISEL [a] x y cmp)
416 (CondSelect x y (SETBCR [a] cmp)) => (ISEL [a+4] x y cmp)
417 // Only lower after bool is lowered. It should always lower. This helps ensure the folding below happens reliably.
418 (CondSelect x y bool) && flagArg(bool) == nil => (ISEL [6] x y (CMPconst [0] (ANDconst [1] bool)))
419 // Fold any CR -> GPR -> CR transfers when applying the above rule.
420 (ISEL [6] x y (CMPconst [0] (ANDconst [1] (SETBC [c] cmp)))) => (ISEL [c] x y cmp)
421 (ISEL [6] x y ((CMP|CMPW)const [0] (SETBC [c] cmp))) => (ISEL [c] x y cmp)
422 (ISEL [6] x y ((CMP|CMPW)const [0] (SETBCR [c] cmp))) => (ISEL [c+4] x y cmp)
423
424 // Lowering loads
425 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
426 (Load <t> ptr mem) && is32BitInt(t) && t.IsSigned() => (MOVWload ptr mem)
427 (Load <t> ptr mem) && is32BitInt(t) && !t.IsSigned() => (MOVWZload ptr mem)
428 (Load <t> ptr mem) && is16BitInt(t) && t.IsSigned() => (MOVHload ptr mem)
429 (Load <t> ptr mem) && is16BitInt(t) && !t.IsSigned() => (MOVHZload ptr mem)
430 (Load <t> ptr mem) && t.IsBoolean() => (MOVBZload ptr mem)
431 (Load <t> ptr mem) && is8BitInt(t) && t.IsSigned() => (MOVBreg (MOVBZload ptr mem)) // PPC has no signed-byte load.
432 (Load <t> ptr mem) && is8BitInt(t) && !t.IsSigned() => (MOVBZload ptr mem)
433
434 (Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
435 (Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
436
437 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
438 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
439 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
440 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
441 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
442 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
443
444 // Using Zero instead of LoweredZero allows the
445 // target address to be folded where possible.
446 (Zero [0] _ mem) => mem
447 (Zero [1] destptr mem) => (MOVBstorezero destptr mem)
448 (Zero [2] destptr mem) =>
449 (MOVHstorezero destptr mem)
450 (Zero [3] destptr mem) =>
451 (MOVBstorezero [2] destptr
452 (MOVHstorezero destptr mem))
453 (Zero [4] destptr mem) =>
454 (MOVWstorezero destptr mem)
455 (Zero [5] destptr mem) =>
456 (MOVBstorezero [4] destptr
457 (MOVWstorezero destptr mem))
458 (Zero [6] destptr mem) =>
459 (MOVHstorezero [4] destptr
460 (MOVWstorezero destptr mem))
461 (Zero [7] destptr mem) =>
462 (MOVBstorezero [6] destptr
463 (MOVHstorezero [4] destptr
464 (MOVWstorezero destptr mem)))
465
466 (Zero [8] {t} destptr mem) => (MOVDstorezero destptr mem)
467 (Zero [12] {t} destptr mem) =>
468 (MOVWstorezero [8] destptr
469 (MOVDstorezero [0] destptr mem))
470 (Zero [16] {t} destptr mem) =>
471 (MOVDstorezero [8] destptr
472 (MOVDstorezero [0] destptr mem))
473 (Zero [24] {t} destptr mem) =>
474 (MOVDstorezero [16] destptr
475 (MOVDstorezero [8] destptr
476 (MOVDstorezero [0] destptr mem)))
477 (Zero [32] {t} destptr mem) =>
478 (MOVDstorezero [24] destptr
479 (MOVDstorezero [16] destptr
480 (MOVDstorezero [8] destptr
481 (MOVDstorezero [0] destptr mem))))
482
483 // Handle cases not handled above
484 // Lowered Short cases do not generate loops, and as a result don't clobber
485 // the address registers or flags.
486 (Zero [s] ptr mem) && buildcfg.GOPPC64 <= 8 && s < 64 => (LoweredZeroShort [s] ptr mem)
487 (Zero [s] ptr mem) && buildcfg.GOPPC64 <= 8 => (LoweredZero [s] ptr mem)
488 (Zero [s] ptr mem) && s < 128 && buildcfg.GOPPC64 >= 9 => (LoweredQuadZeroShort [s] ptr mem)
489 (Zero [s] ptr mem) && buildcfg.GOPPC64 >= 9 => (LoweredQuadZero [s] ptr mem)
490
491 // moves
492 (Move [0] _ _ mem) => mem
493 (Move [1] dst src mem) => (MOVBstore dst (MOVBZload src mem) mem)
494 (Move [2] dst src mem) =>
495 (MOVHstore dst (MOVHZload src mem) mem)
496 (Move [4] dst src mem) =>
497 (MOVWstore dst (MOVWZload src mem) mem)
498 // MOVD for load and store must have offsets that are multiple of 4
499 (Move [8] {t} dst src mem) =>
500 (MOVDstore dst (MOVDload src mem) mem)
501 (Move [3] dst src mem) =>
502 (MOVBstore [2] dst (MOVBZload [2] src mem)
503 (MOVHstore dst (MOVHload src mem) mem))
504 (Move [5] dst src mem) =>
505 (MOVBstore [4] dst (MOVBZload [4] src mem)
506 (MOVWstore dst (MOVWZload src mem) mem))
507 (Move [6] dst src mem) =>
508 (MOVHstore [4] dst (MOVHZload [4] src mem)
509 (MOVWstore dst (MOVWZload src mem) mem))
510 (Move [7] dst src mem) =>
511 (MOVBstore [6] dst (MOVBZload [6] src mem)
512 (MOVHstore [4] dst (MOVHZload [4] src mem)
513 (MOVWstore dst (MOVWZload src mem) mem)))
514
515 // Large move uses a loop. Since the address is computed and the
516 // offset is zero, any alignment can be used.
517 (Move [s] dst src mem) && s > 8 && buildcfg.GOPPC64 <= 8 && logLargeCopy(v, s) =>
518 (LoweredMove [s] dst src mem)
519 (Move [s] dst src mem) && s > 8 && s <= 64 && buildcfg.GOPPC64 >= 9 =>
520 (LoweredQuadMoveShort [s] dst src mem)
521 (Move [s] dst src mem) && s > 8 && buildcfg.GOPPC64 >= 9 && logLargeCopy(v, s) =>
522 (LoweredQuadMove [s] dst src mem)
523
524 // Calls
525 // Lowering calls
526 (StaticCall ...) => (CALLstatic ...)
527 (ClosureCall ...) => (CALLclosure ...)
528 (InterCall ...) => (CALLinter ...)
529 (TailCall ...) => (CALLtail ...)
530
531 // Miscellaneous
532 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
533 (GetCallerSP ...) => (LoweredGetCallerSP ...)
534 (GetCallerPC ...) => (LoweredGetCallerPC ...)
535 (IsNonNil ptr) => (NotEqual (CMPconst [0] ptr))
536 (IsInBounds idx len) => (LessThan (CMPU idx len))
537 (IsSliceInBounds idx len) => (LessEqual (CMPU idx len))
538 (NilCheck ...) => (LoweredNilCheck ...)
539
540 // Write barrier.
541 (WB ...) => (LoweredWB ...)
542
543 // Publication barrier as intrinsic
544 (PubBarrier ...) => (LoweredPubBarrier ...)
545
546 (PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
547 (PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
548 (PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
549
550 // Optimizations
551 // Note that PPC "logical" immediates come in 0:15 and 16:31 unsigned immediate forms,
552 // so ORconst, XORconst easily expand into a pair.
553
554 // Include very-large constants in the const-const case.
555 (AND (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c&d])
556 (OR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c|d])
557 (XOR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c^d])
558 (ORN (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c|^d])
559 (ANDN (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c&^d])
560 (NOR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [^(c|d)])
561
562 // Discover consts
563 (AND x (MOVDconst [-1])) => x
564 (AND x (MOVDconst [c])) && isU16Bit(c) => (ANDconst [c] x)
565 (XOR x (MOVDconst [c])) && isU32Bit(c) => (XORconst [c] x)
566 (OR x (MOVDconst [c])) && isU32Bit(c) => (ORconst [c] x)
567
568 // Simplify consts
569 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
570 (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x)
571 (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x)
572 (ANDconst [-1] x) => x
573 (ANDconst [0] _) => (MOVDconst [0])
574 (XORconst [0] x) => x
575 (ORconst [-1] _) => (MOVDconst [-1])
576 (ORconst [0] x) => x
577
578 // zero-extend of small and => small and
579 (MOVBZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFF => y
580 (MOVHZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFF => y
581 (MOVWZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFFFFFF => y
582 (MOVWZreg y:(AND (MOVDconst [c]) _)) && uint64(c) <= 0xFFFFFFFF => y
583
584 // sign extend of small-positive and => small-positive-and
585 (MOVBreg y:(ANDconst [c] _)) && uint64(c) <= 0x7F => y
586 (MOVHreg y:(ANDconst [c] _)) && uint64(c) <= 0x7FFF => y
587 (MOVWreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFF => y // 0xFFFF is largest immediate constant, when regarded as 32-bit is > 0
588 (MOVWreg y:(AND (MOVDconst [c]) _)) && uint64(c) <= 0x7FFFFFFF => y
589
590 // small and of zero-extend => either zero-extend or small and
591 (ANDconst [c] y:(MOVBZreg _)) && c&0xFF == 0xFF => y
592 (ANDconst [0xFF] (MOVBreg x)) => (MOVBZreg x)
593 (ANDconst [c] y:(MOVHZreg _)) && c&0xFFFF == 0xFFFF => y
594 (ANDconst [0xFFFF] (MOVHreg x)) => (MOVHZreg x)
595
596 (AND (MOVDconst [c]) y:(MOVWZreg _)) && c&0xFFFFFFFF == 0xFFFFFFFF => y
597 (AND (MOVDconst [0xFFFFFFFF]) y:(MOVWreg x)) => (MOVWZreg x)
598 // normal case
599 (ANDconst [c] (MOVBZreg x)) => (ANDconst [c&0xFF] x)
600 (ANDconst [c] (MOVHZreg x)) => (ANDconst [c&0xFFFF] x)
601 (ANDconst [c] (MOVWZreg x)) => (ANDconst [c&0xFFFFFFFF] x)
602
603 // Eliminate unnecessary sign/zero extend following right shift
604 (MOV(B|H|W)Zreg (SRWconst [c] (MOVBZreg x))) => (SRWconst [c] (MOVBZreg x))
605 (MOV(H|W)Zreg (SRWconst [c] (MOVHZreg x))) => (SRWconst [c] (MOVHZreg x))
606 (MOVWZreg (SRWconst [c] (MOVWZreg x))) => (SRWconst [c] (MOVWZreg x))
607 (MOV(B|H|W)reg (SRAWconst [c] (MOVBreg x))) => (SRAWconst [c] (MOVBreg x))
608 (MOV(H|W)reg (SRAWconst [c] (MOVHreg x))) => (SRAWconst [c] (MOVHreg x))
609 (MOVWreg (SRAWconst [c] (MOVWreg x))) => (SRAWconst [c] (MOVWreg x))
610
611 (MOV(WZ|W)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) <= 32 => (S(R|RA)Wconst [c] x)
612 (MOV(HZ|H)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) <= 16 => (S(R|RA)Wconst [c] x)
613 (MOV(BZ|B)reg (S(R|RA)Wconst [c] x)) && sizeof(x.Type) == 8 => (S(R|RA)Wconst [c] x)
614
615 // initial right shift will handle sign/zero extend
616 (MOVBZreg (SRDconst [c] x)) && c>=56 => (SRDconst [c] x)
617 (MOVBreg (SRDconst [c] x)) && c>56 => (SRDconst [c] x)
618 (MOVBreg (SRDconst [c] x)) && c==56 => (SRADconst [c] x)
619 (MOVBreg (SRADconst [c] x)) && c>=56 => (SRADconst [c] x)
620 (MOVBZreg (SRWconst [c] x)) && c>=24 => (SRWconst [c] x)
621 (MOVBreg (SRWconst [c] x)) && c>24 => (SRWconst [c] x)
622 (MOVBreg (SRWconst [c] x)) && c==24 => (SRAWconst [c] x)
623 (MOVBreg (SRAWconst [c] x)) && c>=24 => (SRAWconst [c] x)
624
625 (MOVHZreg (SRDconst [c] x)) && c>=48 => (SRDconst [c] x)
626 (MOVHreg (SRDconst [c] x)) && c>48 => (SRDconst [c] x)
627 (MOVHreg (SRDconst [c] x)) && c==48 => (SRADconst [c] x)
628 (MOVHreg (SRADconst [c] x)) && c>=48 => (SRADconst [c] x)
629 (MOVHZreg (SRWconst [c] x)) && c>=16 => (SRWconst [c] x)
630 (MOVHreg (SRWconst [c] x)) && c>16 => (SRWconst [c] x)
631 (MOVHreg (SRAWconst [c] x)) && c>=16 => (SRAWconst [c] x)
632 (MOVHreg (SRWconst [c] x)) && c==16 => (SRAWconst [c] x)
633
634 (MOVWZreg (SRDconst [c] x)) && c>=32 => (SRDconst [c] x)
635 (MOVWreg (SRDconst [c] x)) && c>32 => (SRDconst [c] x)
636 (MOVWreg (SRADconst [c] x)) && c>=32 => (SRADconst [c] x)
637 (MOVWreg (SRDconst [c] x)) && c==32 => (SRADconst [c] x)
638
639 // Various redundant zero/sign extension combinations.
640 (MOVBZreg y:(MOVBZreg _)) => y // repeat
641 (MOVBreg y:(MOVBreg _)) => y // repeat
642 (MOVBreg (MOVBZreg x)) => (MOVBreg x)
643 (MOVBZreg (MOVBreg x)) => (MOVBZreg x)
644
645 // Catch any remaining rotate+shift cases
646 (MOVBZreg (SRWconst x [s])) && mergePPC64AndSrwi(0xFF,s) != 0 => (RLWINM [mergePPC64AndSrwi(0xFF,s)] x)
647 (MOVBZreg (RLWINM [r] y)) && mergePPC64AndRlwinm(0xFF,r) != 0 => (RLWINM [mergePPC64AndRlwinm(0xFF,r)] y)
648 (MOVHZreg (RLWINM [r] y)) && mergePPC64AndRlwinm(0xFFFF,r) != 0 => (RLWINM [mergePPC64AndRlwinm(0xFFFF,r)] y)
649 (MOVWZreg (RLWINM [r] y)) && mergePPC64MovwzregRlwinm(r) != 0 => (RLWINM [mergePPC64MovwzregRlwinm(r)] y)
650 (ANDconst [m] (RLWINM [r] y)) && mergePPC64AndRlwinm(uint32(m),r) != 0 => (RLWINM [mergePPC64AndRlwinm(uint32(m),r)] y)
651 (SLDconst [s] (RLWINM [r] y)) && mergePPC64SldiRlwinm(s,r) != 0 => (RLWINM [mergePPC64SldiRlwinm(s,r)] y)
652 (RLWINM [r] (MOVHZreg u)) && mergePPC64RlwinmAnd(r,0xFFFF) != 0 => (RLWINM [mergePPC64RlwinmAnd(r,0xFFFF)] u)
653 (RLWINM [r] (ANDconst [a] u)) && mergePPC64RlwinmAnd(r,uint32(a)) != 0 => (RLWINM [mergePPC64RlwinmAnd(r,uint32(a))] u)
654 // SLWconst is a special case of RLWNM which always zero-extends the result.
655 (SLWconst [s] (MOVWZreg w)) => (SLWconst [s] w)
656 (MOVWZreg w:(SLWconst u)) => w
657
658 // H - there are more combinations than these
659
660 (MOVHZreg y:(MOV(H|B)Zreg _)) => y // repeat
661 (MOVHZreg y:(MOVHBRload _ _)) => y
662
663 (MOVHreg y:(MOV(H|B)reg _)) => y // repeat
664
665 (MOV(H|HZ)reg y:(MOV(HZ|H)reg x)) => (MOV(H|HZ)reg x)
666
667 // W - there are more combinations than these
668
669 (MOV(WZ|WZ|WZ|W|W|W)reg y:(MOV(WZ|HZ|BZ|W|H|B)reg _)) => y // repeat
670 (MOVWZreg y:(MOV(H|W)BRload _ _)) => y
671
672 (MOV(W|WZ)reg y:(MOV(WZ|W)reg x)) => (MOV(W|WZ)reg x)
673
674 // Truncate then logical then truncate: omit first, lesser or equal truncate
675 (MOVWZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVWZreg ((OR|XOR|AND) <t> x y))
676 (MOVHZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVHZreg ((OR|XOR|AND) <t> x y))
677 (MOVHZreg ((OR|XOR|AND) <t> x (MOVHZreg y))) => (MOVHZreg ((OR|XOR|AND) <t> x y))
678 (MOVBZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
679 (MOVBZreg ((OR|XOR|AND) <t> x (MOVHZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
680 (MOVBZreg ((OR|XOR|AND) <t> x (MOVBZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
681
682 (MOV(B|H|W)Zreg z:(ANDconst [c] (MOVBZload ptr x))) => z
683 (MOV(B|H|W)Zreg z:(AND y (MOV(B|H|W)Zload ptr x))) => z
684 (MOV(H|W)Zreg z:(ANDconst [c] (MOVHZload ptr x))) => z
685 (MOVWZreg z:(ANDconst [c] (MOVWZload ptr x))) => z
686
687 // Arithmetic constant ops
688
689 (ADD x (MOVDconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDconst [c] x)
690 (ADDconst [c] (ADDconst [d] x)) && is32Bit(c+d) => (ADDconst [c+d] x)
691 (ADDconst [0] x) => x
692 (SUB x (MOVDconst [c])) && is32Bit(-c) => (ADDconst [-c] x)
693
694 (ADDconst [c] (MOVDaddr [d] {sym} x)) && is32Bit(c+int64(d)) => (MOVDaddr [int32(c+int64(d))] {sym} x)
695 (ADDconst [c] x:(SP)) && is32Bit(c) => (MOVDaddr [int32(c)] x) // so it is rematerializeable
696
697 (MULL(W|D) x (MOVDconst [c])) && is16Bit(c) => (MULL(W|D)const [int32(c)] x)
698
699 // Subtract from (with carry, but ignored) constant.
700 // Note, these clobber the carry bit.
701 (SUB (MOVDconst [c]) x) && is32Bit(c) => (SUBFCconst [c] x)
702 (SUBFCconst [c] (NEG x)) => (ADDconst [c] x)
703 (SUBFCconst [c] (SUBFCconst [d] x)) && is32Bit(c-d) => (ADDconst [c-d] x)
704 (SUBFCconst [0] x) => (NEG x)
705 (ADDconst [c] (SUBFCconst [d] x)) && is32Bit(c+d) => (SUBFCconst [c+d] x)
706 (NEG (ADDconst [c] x)) && is32Bit(-c) => (SUBFCconst [-c] x)
707 (NEG (SUBFCconst [c] x)) && is32Bit(-c) => (ADDconst [-c] x)
708 (NEG (SUB x y)) => (SUB y x)
709 (NEG (NEG x)) => x
710
711 // Use register moves instead of stores and loads to move int<=>float values
712 // Common with math Float64bits, Float64frombits
713 (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) => (MFVSRD x)
714 (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) => (MTVSRD x)
715
716 (FMOVDstore [off] {sym} ptr (MTVSRD x) mem) => (MOVDstore [off] {sym} ptr x mem)
717 (MOVDstore [off] {sym} ptr (MFVSRD x) mem) => (FMOVDstore [off] {sym} ptr x mem)
718
719 (MTVSRD (MOVDconst [c])) && !math.IsNaN(math.Float64frombits(uint64(c))) => (FMOVDconst [math.Float64frombits(uint64(c))])
720 (MFVSRD (FMOVDconst [c])) => (MOVDconst [int64(math.Float64bits(c))])
721
722 (MTVSRD x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (FMOVDload [off] {sym} ptr mem)
723 (MFVSRD x:(FMOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVDload [off] {sym} ptr mem)
724
725 // Rules for MOV* or FMOV* ops determine when indexed (MOV*loadidx or MOV*storeidx)
726 // or non-indexed (MOV*load or MOV*store) should be used. Indexed instructions
727 // require an extra instruction and register to load the index so non-indexed is preferred.
728 // Indexed ops generate indexed load or store instructions for all GOPPC64 values.
729 // Non-indexed ops generate DS-form loads and stores when the offset fits in 16 bits,
730 // and on power8 and power9, a multiple of 4 is required for MOVW and MOVD ops.
731 // On power10, prefixed loads and stores can be used for offsets > 16 bits and <= 32 bits.
732 // and support for PC relative addressing must be available if relocation is needed.
733 // On power10, the assembler will determine when to use DS-form or prefixed
734 // instructions for non-indexed ops depending on the value of the offset.
735 //
736 // Fold offsets for stores.
737 (MOV(D|W|H|B)store [off1] {sym} (ADDconst [off2] x) val mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (MOV(D|W|H|B)store [off1+int32(off2)] {sym} x val mem)
738
739 (FMOV(S|D)store [off1] {sym} (ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (FMOV(S|D)store [off1+int32(off2)] {sym} ptr val mem)
740
741 // Fold address into load/store.
742 // If power10 with PCRel is not available, then
743 // the assembler needs to generate several instructions and use
744 // temp register for accessing global, and each time it will reload
745 // the temp register. So don't fold address of global in that case if there is more than
746 // one use.
747 (MOV(B|H|W|D)store [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
748 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
749 (MOV(B|H|W|D)store [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
750
751 (FMOV(S|D)store [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
752 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
753 (FMOV(S|D)store [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
754
755 (MOV(B|H|W)Zload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
756 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
757 (MOV(B|H|W)Zload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
758 (MOV(H|W|D)load [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
759 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
760 (MOV(H|W|D)load [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
761 (FMOV(S|D)load [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
762 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
763 (FMOV(S|D)load [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
764
765 // Fold offsets for loads.
766 (FMOV(S|D)load [off1] {sym} (ADDconst [off2] ptr) mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (FMOV(S|D)load [off1+int32(off2)] {sym} ptr mem)
767
768 (MOV(D|W|WZ|H|HZ|BZ)load [off1] {sym} (ADDconst [off2] x) mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (MOV(D|W|WZ|H|HZ|BZ)load [off1+int32(off2)] {sym} x mem)
769
770 // Determine load + addressing that can be done as a register indexed load
771 (MOV(D|W|WZ|H|HZ|BZ)load [0] {sym} p:(ADD ptr idx) mem) && sym == nil && p.Uses == 1 => (MOV(D|W|WZ|H|HZ|BZ)loadidx ptr idx mem)
772
773 // See comments above concerning selection of indexed vs. non-indexed ops.
774 // These cases don't have relocation.
775 (MOV(D|W)loadidx ptr (MOVDconst [c]) mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(D|W)load [int32(c)] ptr mem)
776 (MOV(WZ|H|HZ|BZ)loadidx ptr (MOVDconst [c]) mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(WZ|H|HZ|BZ)load [int32(c)] ptr mem)
777 (MOV(D|W)loadidx (MOVDconst [c]) ptr mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(D|W)load [int32(c)] ptr mem)
778 (MOV(WZ|H|HZ|BZ)loadidx (MOVDconst [c]) ptr mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(WZ|H|HZ|BZ)load [int32(c)] ptr mem)
779
780 // Store of zero => storezero
781 (MOV(D|W|H|B)store [off] {sym} ptr (MOVDconst [0]) mem) => (MOV(D|W|H|B)storezero [off] {sym} ptr mem)
782
783 // Fold offsets for storezero
784 (MOV(D|W|H|B)storezero [off1] {sym} (ADDconst [off2] x) mem) && ((supportsPPC64PCRel() && is32Bit(int64(off1)+off2)) || (is16Bit(int64(off1)+off2))) =>
785 (MOV(D|W|H|B)storezero [off1+int32(off2)] {sym} x mem)
786
787 // Stores with addressing that can be done as indexed stores
788 (MOV(D|W|H|B)store [0] {sym} p:(ADD ptr idx) val mem) && sym == nil && p.Uses == 1 => (MOV(D|W|H|B)storeidx ptr idx val mem)
789
790 (MOVDstoreidx ptr (MOVDconst [c]) val mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOVDstore [int32(c)] ptr val mem)
791 (MOV(W|H|B)storeidx ptr (MOVDconst [c]) val mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(W|H|B)store [int32(c)] ptr val mem)
792 (MOVDstoreidx (MOVDconst [c]) ptr val mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOVDstore [int32(c)] ptr val mem)
793 (MOV(W|H|B)storeidx (MOVDconst [c]) ptr val mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(W|H|B)store [int32(c)] ptr val mem)
794
795 // Fold symbols into storezero
796 (MOV(D|W|H|B)storezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2)
797 && ((is16Bit(int64(off1+off2)) && (x.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
798 (MOV(D|W|H|B)storezero [off1+off2] {mergeSym(sym1,sym2)} x mem)
799
800 // atomic intrinsics
801 (AtomicLoad(8|32|64|Ptr) ptr mem) => (LoweredAtomicLoad(8|32|64|Ptr) [1] ptr mem)
802 (AtomicLoadAcq(32|64) ptr mem) => (LoweredAtomicLoad(32|64) [0] ptr mem)
803
804 (AtomicStore(8|32|64) ptr val mem) => (LoweredAtomicStore(8|32|64) [1] ptr val mem)
805 (AtomicStoreRel(32|64) ptr val mem) => (LoweredAtomicStore(32|64) [0] ptr val mem)
806
807 (AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...)
808
809 (AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
810
811 (AtomicCompareAndSwap(32|64) ptr old new_ mem) => (LoweredAtomicCas(32|64) [1] ptr old new_ mem)
812 (AtomicCompareAndSwapRel32 ptr old new_ mem) => (LoweredAtomicCas32 [0] ptr old new_ mem)
813
814 (AtomicAnd(8|32) ...) => (LoweredAtomicAnd(8|32) ...)
815 (AtomicOr(8|32) ...) => (LoweredAtomicOr(8|32) ...)
816
817 (Slicemask <t> x) => (SRADconst (NEG <t> x) [63])
818 (ANDconst [1] z:(SRADconst [63] x)) && z.Uses == 1 => (SRDconst [63] x)
819
820 // Note that MOV??reg returns a 64-bit int, x is not necessarily that wide
821 // This may interact with other patterns in the future. (Compare with arm64)
822 (MOV(B|H|W)Zreg x:(MOVBZload _ _)) => x
823 (MOV(B|H|W)Zreg x:(MOVBZloadidx _ _ _)) => x
824 (MOV(H|W)Zreg x:(MOVHZload _ _)) => x
825 (MOV(H|W)Zreg x:(MOVHZloadidx _ _ _)) => x
826 (MOV(H|W)reg x:(MOVHload _ _)) => x
827 (MOV(H|W)reg x:(MOVHloadidx _ _ _)) => x
828 (MOV(WZ|W)reg x:(MOV(WZ|W)load _ _)) => x
829 (MOV(WZ|W)reg x:(MOV(WZ|W)loadidx _ _ _)) => x
830 (MOV(B|W)Zreg x:(Select0 (LoweredAtomicLoad(8|32) _ _))) => x
831
832 // don't extend if argument is already extended
833 (MOVBreg x:(Arg <t>)) && is8BitInt(t) && t.IsSigned() => x
834 (MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !t.IsSigned() => x
835 (MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && t.IsSigned() => x
836 (MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !t.IsSigned() => x
837 (MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && t.IsSigned() => x
838 (MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !t.IsSigned() => x
839
840 (MOVBZreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))])
841 (MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))])
842 (MOVHZreg (MOVDconst [c])) => (MOVDconst [int64(uint16(c))])
843 (MOVHreg (MOVDconst [c])) => (MOVDconst [int64(int16(c))])
844 (MOVWreg (MOVDconst [c])) => (MOVDconst [int64(int32(c))])
845 (MOVWZreg (MOVDconst [c])) => (MOVDconst [int64(uint32(c))])
846
847 // Implement clrsldi and clrslwi extended mnemonics as described in
848 // ISA 3.0 section C.8. AuxInt field contains values needed for
849 // the instructions, packed together since there is only one available.
850 (SLDconst [c] z:(MOVBZreg x)) && c < 8 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,56,63,64)] x)
851 (SLDconst [c] z:(MOVHZreg x)) && c < 16 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,48,63,64)] x)
852 (SLDconst [c] z:(MOVWZreg x)) && c < 32 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,32,63,64)] x)
853
854 (SLDconst [c] z:(ANDconst [d] x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c <= (64-getPPC64ShiftMaskLength(d)) => (CLRLSLDI [newPPC64ShiftAuxInt(c,64-getPPC64ShiftMaskLength(d),63,64)] x)
855 (SLDconst [c] z:(AND (MOVDconst [d]) x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(64-getPPC64ShiftMaskLength(d)) => (CLRLSLDI [newPPC64ShiftAuxInt(c,64-getPPC64ShiftMaskLength(d),63,64)] x)
856 (SLWconst [c] z:(MOVBZreg x)) && z.Uses == 1 && c < 8 => (CLRLSLWI [newPPC64ShiftAuxInt(c,24,31,32)] x)
857 (SLWconst [c] z:(MOVHZreg x)) && z.Uses == 1 && c < 16 => (CLRLSLWI [newPPC64ShiftAuxInt(c,16,31,32)] x)
858 (SLWconst [c] z:(ANDconst [d] x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d)) => (CLRLSLWI [newPPC64ShiftAuxInt(c,32-getPPC64ShiftMaskLength(d),31,32)] x)
859 (SLWconst [c] z:(AND (MOVDconst [d]) x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d)) => (CLRLSLWI [newPPC64ShiftAuxInt(c,32-getPPC64ShiftMaskLength(d),31,32)] x)
860 // special case for power9
861 (SL(W|D)const [c] z:(MOVWreg x)) && c < 32 && buildcfg.GOPPC64 >= 9 => (EXTSWSLconst [c] x)
862
863 // Lose widening ops fed to stores
864 (MOVBstore [off] {sym} ptr (MOV(B|BZ|H|HZ|W|WZ)reg x) mem) => (MOVBstore [off] {sym} ptr x mem)
865 (MOVHstore [off] {sym} ptr (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHstore [off] {sym} ptr x mem)
866 (MOVWstore [off] {sym} ptr (MOV(W|WZ)reg x) mem) => (MOVWstore [off] {sym} ptr x mem)
867 (MOVBstore [off] {sym} ptr (SRWconst (MOV(H|HZ)reg x) [c]) mem) && c <= 8 => (MOVBstore [off] {sym} ptr (SRWconst <typ.UInt32> x [c]) mem)
868 (MOVBstore [off] {sym} ptr (SRWconst (MOV(W|WZ)reg x) [c]) mem) && c <= 24 => (MOVBstore [off] {sym} ptr (SRWconst <typ.UInt32> x [c]) mem)
869 (MOVBstoreidx ptr idx (MOV(B|BZ|H|HZ|W|WZ)reg x) mem) => (MOVBstoreidx ptr idx x mem)
870 (MOVHstoreidx ptr idx (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHstoreidx ptr idx x mem)
871 (MOVWstoreidx ptr idx (MOV(W|WZ)reg x) mem) => (MOVWstoreidx ptr idx x mem)
872 (MOVBstoreidx ptr idx (SRWconst (MOV(H|HZ)reg x) [c]) mem) && c <= 8 => (MOVBstoreidx ptr idx (SRWconst <typ.UInt32> x [c]) mem)
873 (MOVBstoreidx ptr idx (SRWconst (MOV(W|WZ)reg x) [c]) mem) && c <= 24 => (MOVBstoreidx ptr idx (SRWconst <typ.UInt32> x [c]) mem)
874 (MOVHBRstore ptr (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHBRstore ptr x mem)
875 (MOVWBRstore ptr (MOV(W|WZ)reg x) mem) => (MOVWBRstore ptr x mem)
876
877 // Lose W-widening ops fed to compare-W
878 (CMP(W|WU) x (MOV(W|WZ)reg y)) => (CMP(W|WU) x y)
879 (CMP(W|WU) (MOV(W|WZ)reg x) y) => (CMP(W|WU) x y)
880
881 (CMP x (MOVDconst [c])) && is16Bit(c) => (CMPconst x [c])
882 (CMP (MOVDconst [c]) y) && is16Bit(c) => (InvertFlags (CMPconst y [c]))
883 (CMPW x (MOVDconst [c])) && is16Bit(c) => (CMPWconst x [int32(c)])
884 (CMPW (MOVDconst [c]) y) && is16Bit(c) => (InvertFlags (CMPWconst y [int32(c)]))
885
886 (CMPU x (MOVDconst [c])) && isU16Bit(c) => (CMPUconst x [c])
887 (CMPU (MOVDconst [c]) y) && isU16Bit(c) => (InvertFlags (CMPUconst y [c]))
888 (CMPWU x (MOVDconst [c])) && isU16Bit(c) => (CMPWUconst x [int32(c)])
889 (CMPWU (MOVDconst [c]) y) && isU16Bit(c) => (InvertFlags (CMPWUconst y [int32(c)]))
890
891 // Canonicalize the order of arguments to comparisons - helps with CSE.
892 ((CMP|CMPW|CMPU|CMPWU) x y) && canonLessThan(x,y) => (InvertFlags ((CMP|CMPW|CMPU|CMPWU) y x))
893
894 // n is always a zero-extended uint16 value, so n & z is always a non-negative 32 or 64 bit value.
895 // Rewrite to a cmp int64(0) to lower into ANDCCconst in the latelower pass.
896 (CMP(W|U|WU)const [0] a:(ANDconst [n] z)) => (CMPconst [0] a)
897
898 // SETBC auxInt values 0=LT 1=GT 2=EQ Crbit==1 ? 1 : 0
899 // SETBCR auxInt values 0=LT 1=GT 2=EQ Crbit==1 ? 0 : 1
900 (Equal cmp) => (SETBC [2] cmp)
901 (NotEqual cmp) => (SETBCR [2] cmp)
902 (LessThan cmp) => (SETBC [0] cmp)
903 (FLessThan cmp) => (SETBC [0] cmp)
904 (FLessEqual cmp) => (OR (SETBC [2] cmp) (SETBC [0] cmp))
905 (GreaterEqual cmp) => (SETBCR [0] cmp)
906 (GreaterThan cmp) => (SETBC [1] cmp)
907 (FGreaterEqual cmp) => (OR (SETBC [2] cmp) (SETBC [1] cmp))
908 (FGreaterThan cmp) => (SETBC [1] cmp)
909 (LessEqual cmp) => (SETBCR [1] cmp)
910
911 (SETBC [0] (FlagLT)) => (MOVDconst [1])
912 (SETBC [0] (Flag(GT|EQ))) => (MOVDconst [0])
913 (SETBC [1] (FlagGT)) => (MOVDconst [1])
914 (SETBC [1] (Flag(LT|EQ))) => (MOVDconst [0])
915 (SETBC [2] (FlagEQ)) => (MOVDconst [1])
916 (SETBC [2] (Flag(LT|GT))) => (MOVDconst [0])
917
918 (SETBCR [0] (FlagLT)) => (MOVDconst [0])
919 (SETBCR [0] (Flag(GT|EQ))) => (MOVDconst [1])
920 (SETBCR [1] (FlagGT)) => (MOVDconst [0])
921 (SETBCR [1] (Flag(LT|EQ))) => (MOVDconst [1])
922 (SETBCR [2] (FlagEQ)) => (MOVDconst [0])
923 (SETBCR [2] (Flag(LT|GT))) => (MOVDconst [1])
924
925 (SETBC [0] (InvertFlags bool)) => (SETBC [1] bool)
926 (SETBC [1] (InvertFlags bool)) => (SETBC [0] bool)
927 (SETBC [2] (InvertFlags bool)) => (SETBC [2] bool)
928
929 (SETBCR [0] (InvertFlags bool)) => (SETBCR [1] bool)
930 (SETBCR [1] (InvertFlags bool)) => (SETBCR [0] bool)
931 (SETBCR [2] (InvertFlags bool)) => (SETBCR [2] bool)
932
933 // ISEL auxInt values 0=LT 1=GT 2=EQ arg2 ? arg0 : arg1
934 // ISEL auxInt values 4=GE 5=LE 6=NE !arg2 ? arg1 : arg0
935
936 (ISEL [2] x _ (FlagEQ)) => x
937 (ISEL [2] _ y (Flag(LT|GT))) => y
938
939 (ISEL [6] _ y (FlagEQ)) => y
940 (ISEL [6] x _ (Flag(LT|GT))) => x
941
942 (ISEL [0] _ y (Flag(EQ|GT))) => y
943 (ISEL [0] x _ (FlagLT)) => x
944
945 (ISEL [5] _ x (Flag(EQ|LT))) => x
946 (ISEL [5] y _ (FlagGT)) => y
947
948 (ISEL [1] _ y (Flag(EQ|LT))) => y
949 (ISEL [1] x _ (FlagGT)) => x
950
951 (ISEL [4] x _ (Flag(EQ|GT))) => x
952 (ISEL [4] _ y (FlagLT)) => y
953
954 (SETBC [n] (InvertFlags bool)) => (SETBCR [n] bool)
955 (SETBCR [n] (InvertFlags bool)) => (SETBC [n] bool)
956
957 (ISEL [n] x y (InvertFlags bool)) && n%4 == 0 => (ISEL [n+1] x y bool)
958 (ISEL [n] x y (InvertFlags bool)) && n%4 == 1 => (ISEL [n-1] x y bool)
959 (ISEL [n] x y (InvertFlags bool)) && n%4 == 2 => (ISEL [n] x y bool)
960 (XORconst [1] (SETBCR [n] cmp)) => (SETBC [n] cmp)
961 (XORconst [1] (SETBC [n] cmp)) => (SETBCR [n] cmp)
962
963 (SETBC [2] (CMPconst [0] a:(ANDconst [1] _))) => (XORconst [1] a)
964 (SETBCR [2] (CMPconst [0] a:(ANDconst [1] _))) => a
965
966 // Only CMPconst for these in case AND|OR|XOR result is > 32 bits
967 (SETBC [2] (CMPconst [0] a:(AND y z))) && a.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (ANDCC y z )))
968 (SETBCR [2] (CMPconst [0] a:(AND y z))) && a.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (ANDCC y z )))
969
970 (SETBC [2] (CMPconst [0] o:(OR y z))) && o.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (ORCC y z )))
971 (SETBCR [2] (CMPconst [0] o:(OR y z))) && o.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (ORCC y z )))
972
973 (SETBC [2] (CMPconst [0] a:(XOR y z))) && a.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (XORCC y z )))
974 (SETBCR [2] (CMPconst [0] a:(XOR y z))) && a.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (XORCC y z )))
975
976 // A particular pattern seen in cgo code:
977 (AND (MOVDconst [c]) x:(MOVBZload _ _)) => (ANDconst [c&0xFF] x)
978
979 // floating point negative abs
980 (FNEG (F(ABS|NABS) x)) => (F(NABS|ABS) x)
981
982 // floating-point fused multiply-add/sub
983 (F(ADD|SUB) (FMUL x y) z) && x.Block.Func.useFMA(v) => (FM(ADD|SUB) x y z)
984 (F(ADDS|SUBS) (FMULS x y) z) && x.Block.Func.useFMA(v) => (FM(ADDS|SUBS) x y z)
985
986 // Arch-specific inlining for small or disjoint runtime.memmove
987 (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem)))))
988 && sz >= 0
989 && isSameCall(sym, "runtime.memmove")
990 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
991 && isInlinableMemmove(dst, src, sz, config)
992 && clobber(s1, s2, s3, call)
993 => (Move [sz] dst src mem)
994
995 // Match post-lowering calls, register version.
996 (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem))
997 && sz >= 0
998 && isSameCall(sym, "runtime.memmove")
999 && call.Uses == 1
1000 && isInlinableMemmove(dst, src, sz, config)
1001 && clobber(call)
1002 => (Move [sz] dst src mem)
1003
1004 // Prefetch instructions (TH specified using aux field)
1005 // For DCBT Ra,Rb,TH, A value of TH indicates:
1006 // 0, hint this cache line will be used soon. (PrefetchCache)
1007 // 16, hint this cache line will not be used for long. (PrefetchCacheStreamed)
1008 // See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/
1009 (PrefetchCache ptr mem) => (DCBT ptr mem [0])
1010 (PrefetchCacheStreamed ptr mem) => (DCBT ptr mem [16])
1011
1012 // Use byte reverse instructions on Power10
1013 (Bswap(16|32|64) x) && buildcfg.GOPPC64>=10 => (BR(H|W|D) x)
1014
1015 // Fold bit reversal into loads.
1016 (BR(W|H) x:(MOV(W|H)Zload [off] {sym} ptr mem)) && x.Uses == 1 => @x.Block (MOV(W|H)BRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1017 (BR(W|H) x:(MOV(W|H)Zloadidx ptr idx mem)) && x.Uses == 1 => @x.Block (MOV(W|H)BRloadidx ptr idx mem)
1018 (BRD x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 => @x.Block (MOVDBRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1019 (BRD x:(MOVDloadidx ptr idx mem)) && x.Uses == 1 => @x.Block (MOVDBRloadidx ptr idx mem)
1020
1021 // Fold bit reversal into stores.
1022 (MOV(D|W|H)store [off] {sym} ptr r:(BR(D|W|H) val) mem) && r.Uses == 1 => (MOV(D|W|H)BRstore (MOVDaddr <ptr.Type> [off] {sym} ptr) val mem)
1023 (MOV(D|W|H)storeidx ptr idx r:(BR(D|W|H) val) mem) && r.Uses == 1 => (MOV(D|W|H)BRstoreidx ptr idx val mem)
1024
1025 // GOPPC64<10 rules.
1026 // These Bswap operations should only be introduced by the memcombine pass in places where they can be folded into loads or stores.
1027 (Bswap(32|16) x:(MOV(W|H)Zload [off] {sym} ptr mem)) => @x.Block (MOV(W|H)BRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1028 (Bswap(32|16) x:(MOV(W|H)Zloadidx ptr idx mem)) => @x.Block (MOV(W|H)BRloadidx ptr idx mem)
1029 (Bswap64 x:(MOVDload [off] {sym} ptr mem)) => @x.Block (MOVDBRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1030 (Bswap64 x:(MOVDloadidx ptr idx mem)) => @x.Block (MOVDBRloadidx ptr idx mem)
1031 (MOV(D|W|H)store [off] {sym} ptr (Bswap(64|32|16) val) mem) => (MOV(D|W|H)BRstore (MOVDaddr <ptr.Type> [off] {sym} ptr) val mem)
1032 (MOV(D|W|H)storeidx ptr idx (Bswap(64|32|16) val) mem) => (MOV(D|W|H)BRstoreidx ptr idx val mem)
1033
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