// DO NOT EDIT // generated by: ppc64map -fmt=encoder pp64.csv package ppc64 import ( "cmd/internal/obj" ) const ( AXXSETACCZ = ALASTAOUT + iota AXXMTACC AXXMFACC AXXGENPCVWM AXXGENPCVHM AXXGENPCVDM AXXGENPCVBM AXVTLSBB AXVI8GER4SPP AXVI8GER4PP AXVI8GER4 AXVI4GER8PP AXVI4GER8 AXVI16GER2SPP AXVI16GER2S AXVI16GER2PP AXVI16GER2 AXVF64GERPP AXVF64GERPN AXVF64GERNP AXVF64GERNN AXVF64GER AXVF32GERPP AXVF32GERPN AXVF32GERNP AXVF32GERNN AXVF32GER AXVF16GER2PP AXVF16GER2PN AXVF16GER2NP AXVF16GER2NN AXVF16GER2 AXVCVSPBF16 AXVCVBF16SPN AXVBF16GER2PP AXVBF16GER2PN AXVBF16GER2NP AXVBF16GER2NN AXVBF16GER2 AXSMINCQP AXSMAXCQP AXSCVUQQP AXSCVSQQP AXSCVQPUQZ AXSCVQPSQZ AXSCMPGTQP AXSCMPGEQP AXSCMPEQQP AVSTRIHRCC AVSTRIHR AVSTRIHLCC AVSTRIHL AVSTRIBRCC AVSTRIBR AVSTRIBLCC AVSTRIBL AVSRQ AVSRDBI AVSRAQ AVSLQ AVSLDBI AVRLQNM AVRLQMI AVRLQ AVPEXTD AVPDEPD AVMULOUD AVMULOSD AVMULLD AVMULHUW AVMULHUD AVMULHSW AVMULHSD AVMULEUD AVMULESD AVMSUMCUD AVMODUW AVMODUQ AVMODUD AVMODSW AVMODSQ AVMODSD AVINSWVRX AVINSWVLX AVINSWRX AVINSWLX AVINSW AVINSHVRX AVINSHVLX AVINSHRX AVINSHLX AVINSDRX AVINSDLX AVINSD AVINSBVRX AVINSBVLX AVINSBRX AVINSBLX AVGNB AVEXTSD2Q AVEXTRACTWM AVEXTRACTQM AVEXTRACTHM AVEXTRACTDM AVEXTRACTBM AVEXTDUWVRX AVEXTDUWVLX AVEXTDUHVRX AVEXTDUHVLX AVEXTDUBVRX AVEXTDUBVLX AVEXTDDVRX AVEXTDDVLX AVEXPANDWM AVEXPANDQM AVEXPANDHM AVEXPANDDM AVEXPANDBM AVDIVUW AVDIVUQ AVDIVUD AVDIVSW AVDIVSQ AVDIVSD AVDIVEUW AVDIVEUQ AVDIVEUD AVDIVESW AVDIVESQ AVDIVESD AVCTZDM AVCNTMBW AVCNTMBH AVCNTMBD AVCNTMBB AVCMPUQ AVCMPSQ AVCMPGTUQCC AVCMPGTUQ AVCMPGTSQCC AVCMPGTSQ AVCMPEQUQCC AVCMPEQUQ AVCLZDM AVCLRRB AVCLRLB AVCFUGED ASTXVRWX ASTXVRHX ASTXVRDX ASTXVRBX ASTXVPX ASTXVP ASETNBCR ASETNBC ASETBCR ASETBC APEXTD APDEPD AMTVSRWM AMTVSRQM AMTVSRHM AMTVSRDM AMTVSRBMI AMTVSRBM ALXVRWX ALXVRHX ALXVRDX ALXVRBX ALXVPX ALXVP ALXVKQ ADCTFIXQQ ADCFFIXQQ ACNTTZDM ACNTLZDM ACFUGED ABRW ABRH ABRD AHASHSTP AHASHST AHASHCHKP AHASHCHK AXXSPLTIW AXXSPLTIDP AXXSPLTI32DX AXXPERMX AXXEVAL AXXBLENDVW AXXBLENDVH AXXBLENDVD AXXBLENDVB APSTXVP APSTXV APSTXSSP APSTXSD APSTW APSTQ APSTH APSTFS APSTFD APSTD APSTB APNOP APMXVI8GER4SPP APMXVI8GER4PP APMXVI8GER4 APMXVI4GER8PP APMXVI4GER8 APMXVI16GER2SPP APMXVI16GER2S APMXVI16GER2PP APMXVI16GER2 APMXVF64GERPP APMXVF64GERPN APMXVF64GERNP APMXVF64GERNN APMXVF64GER APMXVF32GERPP APMXVF32GERPN APMXVF32GERNP APMXVF32GERNN APMXVF32GER APMXVF16GER2PP APMXVF16GER2PN APMXVF16GER2NP APMXVF16GER2NN APMXVF16GER2 APMXVBF16GER2PP APMXVBF16GER2PN APMXVBF16GER2NP APMXVBF16GER2NN APMXVBF16GER2 APLXVP APLXV APLXSSP APLXSD APLWZ APLWA APLQ APLHZ APLHA APLFS APLFD APLD APLBZ APADDI ALASTGEN AFIRSTGEN = AXXSETACCZ ) var GenAnames = []string{ "XXSETACCZ", "XXMTACC", "XXMFACC", "XXGENPCVWM", "XXGENPCVHM", "XXGENPCVDM", "XXGENPCVBM", "XVTLSBB", "XVI8GER4SPP", "XVI8GER4PP", "XVI8GER4", "XVI4GER8PP", "XVI4GER8", "XVI16GER2SPP", "XVI16GER2S", "XVI16GER2PP", "XVI16GER2", "XVF64GERPP", "XVF64GERPN", "XVF64GERNP", "XVF64GERNN", "XVF64GER", "XVF32GERPP", "XVF32GERPN", "XVF32GERNP", "XVF32GERNN", "XVF32GER", "XVF16GER2PP", "XVF16GER2PN", "XVF16GER2NP", "XVF16GER2NN", "XVF16GER2", "XVCVSPBF16", "XVCVBF16SPN", "XVBF16GER2PP", "XVBF16GER2PN", "XVBF16GER2NP", "XVBF16GER2NN", "XVBF16GER2", "XSMINCQP", "XSMAXCQP", "XSCVUQQP", "XSCVSQQP", "XSCVQPUQZ", "XSCVQPSQZ", "XSCMPGTQP", "XSCMPGEQP", "XSCMPEQQP", "VSTRIHRCC", "VSTRIHR", "VSTRIHLCC", "VSTRIHL", "VSTRIBRCC", "VSTRIBR", "VSTRIBLCC", "VSTRIBL", "VSRQ", "VSRDBI", "VSRAQ", "VSLQ", "VSLDBI", "VRLQNM", "VRLQMI", "VRLQ", "VPEXTD", "VPDEPD", "VMULOUD", "VMULOSD", "VMULLD", "VMULHUW", "VMULHUD", "VMULHSW", "VMULHSD", "VMULEUD", "VMULESD", "VMSUMCUD", "VMODUW", "VMODUQ", "VMODUD", "VMODSW", "VMODSQ", "VMODSD", "VINSWVRX", "VINSWVLX", "VINSWRX", "VINSWLX", "VINSW", "VINSHVRX", "VINSHVLX", "VINSHRX", "VINSHLX", "VINSDRX", "VINSDLX", "VINSD", "VINSBVRX", "VINSBVLX", "VINSBRX", "VINSBLX", "VGNB", "VEXTSD2Q", "VEXTRACTWM", "VEXTRACTQM", "VEXTRACTHM", "VEXTRACTDM", "VEXTRACTBM", "VEXTDUWVRX", "VEXTDUWVLX", "VEXTDUHVRX", "VEXTDUHVLX", "VEXTDUBVRX", "VEXTDUBVLX", "VEXTDDVRX", "VEXTDDVLX", "VEXPANDWM", "VEXPANDQM", "VEXPANDHM", "VEXPANDDM", "VEXPANDBM", "VDIVUW", "VDIVUQ", "VDIVUD", "VDIVSW", "VDIVSQ", "VDIVSD", "VDIVEUW", "VDIVEUQ", "VDIVEUD", "VDIVESW", "VDIVESQ", "VDIVESD", "VCTZDM", "VCNTMBW", "VCNTMBH", "VCNTMBD", "VCNTMBB", "VCMPUQ", "VCMPSQ", "VCMPGTUQCC", "VCMPGTUQ", "VCMPGTSQCC", "VCMPGTSQ", "VCMPEQUQCC", "VCMPEQUQ", "VCLZDM", "VCLRRB", "VCLRLB", "VCFUGED", "STXVRWX", "STXVRHX", "STXVRDX", "STXVRBX", "STXVPX", "STXVP", "SETNBCR", "SETNBC", "SETBCR", "SETBC", "PEXTD", "PDEPD", "MTVSRWM", "MTVSRQM", "MTVSRHM", "MTVSRDM", "MTVSRBMI", "MTVSRBM", "LXVRWX", "LXVRHX", "LXVRDX", "LXVRBX", "LXVPX", "LXVP", "LXVKQ", "DCTFIXQQ", "DCFFIXQQ", "CNTTZDM", "CNTLZDM", "CFUGED", "BRW", "BRH", "BRD", "HASHSTP", "HASHST", "HASHCHKP", "HASHCHK", "XXSPLTIW", "XXSPLTIDP", "XXSPLTI32DX", "XXPERMX", "XXEVAL", "XXBLENDVW", "XXBLENDVH", "XXBLENDVD", "XXBLENDVB", "PSTXVP", "PSTXV", "PSTXSSP", "PSTXSD", "PSTW", "PSTQ", "PSTH", "PSTFS", "PSTFD", "PSTD", "PSTB", "PNOP", "PMXVI8GER4SPP", "PMXVI8GER4PP", "PMXVI8GER4", "PMXVI4GER8PP", "PMXVI4GER8", "PMXVI16GER2SPP", "PMXVI16GER2S", "PMXVI16GER2PP", "PMXVI16GER2", "PMXVF64GERPP", "PMXVF64GERPN", "PMXVF64GERNP", "PMXVF64GERNN", "PMXVF64GER", "PMXVF32GERPP", "PMXVF32GERPN", "PMXVF32GERNP", "PMXVF32GERNN", "PMXVF32GER", "PMXVF16GER2PP", "PMXVF16GER2PN", "PMXVF16GER2NP", "PMXVF16GER2NN", "PMXVF16GER2", "PMXVBF16GER2PP", "PMXVBF16GER2PN", "PMXVBF16GER2NP", "PMXVBF16GER2NN", "PMXVBF16GER2", "PLXVP", "PLXV", "PLXSSP", "PLXSD", "PLWZ", "PLWA", "PLQ", "PLHZ", "PLHA", "PLFS", "PLFD", "PLD", "PLBZ", "PADDI", } var GenOpcodes = [...]uint32{ 0x7c030162, // AXXSETACCZ 0x7c010162, // AXXMTACC 0x7c000162, // AXXMFACC 0xf0000768, // AXXGENPCVWM 0xf000072a, // AXXGENPCVHM 0xf000076a, // AXXGENPCVDM 0xf0000728, // AXXGENPCVBM 0xf002076c, // AXVTLSBB 0xec000318, // AXVI8GER4SPP 0xec000010, // AXVI8GER4PP 0xec000018, // AXVI8GER4 0xec000110, // AXVI4GER8PP 0xec000118, // AXVI4GER8 0xec000150, // AXVI16GER2SPP 0xec000158, // AXVI16GER2S 0xec000358, // AXVI16GER2PP 0xec000258, // AXVI16GER2 0xec0001d0, // AXVF64GERPP 0xec0005d0, // AXVF64GERPN 0xec0003d0, // AXVF64GERNP 0xec0007d0, // AXVF64GERNN 0xec0001d8, // AXVF64GER 0xec0000d0, // AXVF32GERPP 0xec0004d0, // AXVF32GERPN 0xec0002d0, // AXVF32GERNP 0xec0006d0, // AXVF32GERNN 0xec0000d8, // AXVF32GER 0xec000090, // AXVF16GER2PP 0xec000490, // AXVF16GER2PN 0xec000290, // AXVF16GER2NP 0xec000690, // AXVF16GER2NN 0xec000098, // AXVF16GER2 0xf011076c, // AXVCVSPBF16 0xf010076c, // AXVCVBF16SPN 0xec000190, // AXVBF16GER2PP 0xec000590, // AXVBF16GER2PN 0xec000390, // AXVBF16GER2NP 0xec000790, // AXVBF16GER2NN 0xec000198, // AXVBF16GER2 0xfc0005c8, // AXSMINCQP 0xfc000548, // AXSMAXCQP 0xfc030688, // AXSCVUQQP 0xfc0b0688, // AXSCVSQQP 0xfc000688, // AXSCVQPUQZ 0xfc080688, // AXSCVQPSQZ 0xfc0001c8, // AXSCMPGTQP 0xfc000188, // AXSCMPGEQP 0xfc000088, // AXSCMPEQQP 0x1003040d, // AVSTRIHRCC 0x1003000d, // AVSTRIHR 0x1002040d, // AVSTRIHLCC 0x1002000d, // AVSTRIHL 0x1001040d, // AVSTRIBRCC 0x1001000d, // AVSTRIBR 0x1000040d, // AVSTRIBLCC 0x1000000d, // AVSTRIBL 0x10000205, // AVSRQ 0x10000216, // AVSRDBI 0x10000305, // AVSRAQ 0x10000105, // AVSLQ 0x10000016, // AVSLDBI 0x10000145, // AVRLQNM 0x10000045, // AVRLQMI 0x10000005, // AVRLQ 0x1000058d, // AVPEXTD 0x100005cd, // AVPDEPD 0x100000c8, // AVMULOUD 0x100001c8, // AVMULOSD 0x100001c9, // AVMULLD 0x10000289, // AVMULHUW 0x100002c9, // AVMULHUD 0x10000389, // AVMULHSW 0x100003c9, // AVMULHSD 0x100002c8, // AVMULEUD 0x100003c8, // AVMULESD 0x10000017, // AVMSUMCUD 0x1000068b, // AVMODUW 0x1000060b, // AVMODUQ 0x100006cb, // AVMODUD 0x1000078b, // AVMODSW 0x1000070b, // AVMODSQ 0x100007cb, // AVMODSD 0x1000018f, // AVINSWVRX 0x1000008f, // AVINSWVLX 0x1000038f, // AVINSWRX 0x1000028f, // AVINSWLX 0x100000cf, // AVINSW 0x1000014f, // AVINSHVRX 0x1000004f, // AVINSHVLX 0x1000034f, // AVINSHRX 0x1000024f, // AVINSHLX 0x100003cf, // AVINSDRX 0x100002cf, // AVINSDLX 0x100001cf, // AVINSD 0x1000010f, // AVINSBVRX 0x1000000f, // AVINSBVLX 0x1000030f, // AVINSBRX 0x1000020f, // AVINSBLX 0x100004cc, // AVGNB 0x101b0602, // AVEXTSD2Q 0x100a0642, // AVEXTRACTWM 0x100c0642, // AVEXTRACTQM 0x10090642, // AVEXTRACTHM 0x100b0642, // AVEXTRACTDM 0x10080642, // AVEXTRACTBM 0x1000001d, // AVEXTDUWVRX 0x1000001c, // AVEXTDUWVLX 0x1000001b, // AVEXTDUHVRX 0x1000001a, // AVEXTDUHVLX 0x10000019, // AVEXTDUBVRX 0x10000018, // AVEXTDUBVLX 0x1000001f, // AVEXTDDVRX 0x1000001e, // AVEXTDDVLX 0x10020642, // AVEXPANDWM 0x10040642, // AVEXPANDQM 0x10010642, // AVEXPANDHM 0x10030642, // AVEXPANDDM 0x10000642, // AVEXPANDBM 0x1000008b, // AVDIVUW 0x1000000b, // AVDIVUQ 0x100000cb, // AVDIVUD 0x1000018b, // AVDIVSW 0x1000010b, // AVDIVSQ 0x100001cb, // AVDIVSD 0x1000028b, // AVDIVEUW 0x1000020b, // AVDIVEUQ 0x100002cb, // AVDIVEUD 0x1000038b, // AVDIVESW 0x1000030b, // AVDIVESQ 0x100003cb, // AVDIVESD 0x100007c4, // AVCTZDM 0x101c0642, // AVCNTMBW 0x101a0642, // AVCNTMBH 0x101e0642, // AVCNTMBD 0x10180642, // AVCNTMBB 0x10000101, // AVCMPUQ 0x10000141, // AVCMPSQ 0x10000687, // AVCMPGTUQCC 0x10000287, // AVCMPGTUQ 0x10000787, // AVCMPGTSQCC 0x10000387, // AVCMPGTSQ 0x100005c7, // AVCMPEQUQCC 0x100001c7, // AVCMPEQUQ 0x10000784, // AVCLZDM 0x100001cd, // AVCLRRB 0x1000018d, // AVCLRLB 0x1000054d, // AVCFUGED 0x7c00019a, // ASTXVRWX 0x7c00015a, // ASTXVRHX 0x7c0001da, // ASTXVRDX 0x7c00011a, // ASTXVRBX 0x7c00039a, // ASTXVPX 0x18000001, // ASTXVP 0x7c0003c0, // ASETNBCR 0x7c000380, // ASETNBC 0x7c000340, // ASETBCR 0x7c000300, // ASETBC 0x7c000178, // APEXTD 0x7c000138, // APDEPD 0x10120642, // AMTVSRWM 0x10140642, // AMTVSRQM 0x10110642, // AMTVSRHM 0x10130642, // AMTVSRDM 0x10000014, // AMTVSRBMI 0x10100642, // AMTVSRBM 0x7c00009a, // ALXVRWX 0x7c00005a, // ALXVRHX 0x7c0000da, // ALXVRDX 0x7c00001a, // ALXVRBX 0x7c00029a, // ALXVPX 0x18000000, // ALXVP 0xf01f02d0, // ALXVKQ 0xfc0107c4, // ADCTFIXQQ 0xfc0007c4, // ADCFFIXQQ 0x7c000476, // ACNTTZDM 0x7c000076, // ACNTLZDM 0x7c0001b8, // ACFUGED 0x7c000136, // ABRW 0x7c0001b6, // ABRH 0x7c000176, // ABRD 0x7c000524, // AHASHSTP 0x7c0005a4, // AHASHST 0x7c000564, // AHASHCHKP 0x7c0005e4, // AHASHCHK 0x80060000, // AXXSPLTIW 0x80040000, // AXXSPLTIDP 0x80000000, // AXXSPLTI32DX 0x88000000, // AXXPERMX 0x88000010, // AXXEVAL 0x84000020, // AXXBLENDVW 0x84000010, // AXXBLENDVH 0x84000030, // AXXBLENDVD 0x84000000, // AXXBLENDVB 0xf8000000, // APSTXVP 0xd8000000, // APSTXV 0xbc000000, // APSTXSSP 0xb8000000, // APSTXSD 0x90000000, // APSTW 0xf0000000, // APSTQ 0xb0000000, // APSTH 0xd0000000, // APSTFS 0xd8000000, // APSTFD 0xf4000000, // APSTD 0x98000000, // APSTB 0x00000000, // APNOP 0xec000318, // APMXVI8GER4SPP 0xec000010, // APMXVI8GER4PP 0xec000018, // APMXVI8GER4 0xec000110, // APMXVI4GER8PP 0xec000118, // APMXVI4GER8 0xec000150, // APMXVI16GER2SPP 0xec000158, // APMXVI16GER2S 0xec000358, // APMXVI16GER2PP 0xec000258, // APMXVI16GER2 0xec0001d0, // APMXVF64GERPP 0xec0005d0, // APMXVF64GERPN 0xec0003d0, // APMXVF64GERNP 0xec0007d0, // APMXVF64GERNN 0xec0001d8, // APMXVF64GER 0xec0000d0, // APMXVF32GERPP 0xec0004d0, // APMXVF32GERPN 0xec0002d0, // APMXVF32GERNP 0xec0006d0, // APMXVF32GERNN 0xec0000d8, // APMXVF32GER 0xec000090, // APMXVF16GER2PP 0xec000490, // APMXVF16GER2PN 0xec000290, // APMXVF16GER2NP 0xec000690, // APMXVF16GER2NN 0xec000098, // APMXVF16GER2 0xec000190, // APMXVBF16GER2PP 0xec000590, // APMXVBF16GER2PN 0xec000390, // APMXVBF16GER2NP 0xec000790, // APMXVBF16GER2NN 0xec000198, // APMXVBF16GER2 0xe8000000, // APLXVP 0xc8000000, // APLXV 0xac000000, // APLXSSP 0xa8000000, // APLXSD 0x80000000, // APLWZ 0xa4000000, // APLWA 0xe0000000, // APLQ 0xa0000000, // APLHZ 0xa8000000, // APLHA 0xc0000000, // APLFS 0xc8000000, // APLFD 0xe4000000, // APLD 0x88000000, // APLBZ 0x38000000, // APADDI } var GenPfxOpcodes = [...]uint32{ 0x05000000, // AXXSPLTIW 0x05000000, // AXXSPLTIDP 0x05000000, // AXXSPLTI32DX 0x05000000, // AXXPERMX 0x05000000, // AXXEVAL 0x05000000, // AXXBLENDVW 0x05000000, // AXXBLENDVH 0x05000000, // AXXBLENDVD 0x05000000, // AXXBLENDVB 0x04000000, // APSTXVP 0x04000000, // APSTXV 0x04000000, // APSTXSSP 0x04000000, // APSTXSD 0x06000000, // APSTW 0x04000000, // APSTQ 0x06000000, // APSTH 0x06000000, // APSTFS 0x06000000, // APSTFD 0x04000000, // APSTD 0x06000000, // APSTB 0x07000000, // APNOP 0x07900000, // APMXVI8GER4SPP 0x07900000, // APMXVI8GER4PP 0x07900000, // APMXVI8GER4 0x07900000, // APMXVI4GER8PP 0x07900000, // APMXVI4GER8 0x07900000, // APMXVI16GER2SPP 0x07900000, // APMXVI16GER2S 0x07900000, // APMXVI16GER2PP 0x07900000, // APMXVI16GER2 0x07900000, // APMXVF64GERPP 0x07900000, // APMXVF64GERPN 0x07900000, // APMXVF64GERNP 0x07900000, // APMXVF64GERNN 0x07900000, // APMXVF64GER 0x07900000, // APMXVF32GERPP 0x07900000, // APMXVF32GERPN 0x07900000, // APMXVF32GERNP 0x07900000, // APMXVF32GERNN 0x07900000, // APMXVF32GER 0x07900000, // APMXVF16GER2PP 0x07900000, // APMXVF16GER2PN 0x07900000, // APMXVF16GER2NP 0x07900000, // APMXVF16GER2NN 0x07900000, // APMXVF16GER2 0x07900000, // APMXVBF16GER2PP 0x07900000, // APMXVBF16GER2PN 0x07900000, // APMXVBF16GER2NP 0x07900000, // APMXVBF16GER2NN 0x07900000, // APMXVBF16GER2 0x04000000, // APLXVP 0x04000000, // APLXV 0x04000000, // APLXSSP 0x04000000, // APLXSD 0x06000000, // APLWZ 0x04000000, // APLWA 0x04000000, // APLQ 0x06000000, // APLHZ 0x06000000, // APLHA 0x06000000, // APLFS 0x06000000, // APLFD 0x04000000, // APLD 0x06000000, // APLBZ 0x06000000, // APADDI } var optabGen = []Optab{ {as: ABRW, a1: C_REG, a6: C_REG, asmout: type_brw, size: 4}, {as: ADCFFIXQQ, a1: C_VREG, a6: C_FREGP, asmout: type_xscvuqqp, size: 4}, {as: ADCTFIXQQ, a1: C_FREGP, a6: C_VREG, asmout: type_xscvuqqp, size: 4}, {as: AHASHCHKP, a1: C_SOREG, a6: C_REG, asmout: type_hashchkp, size: 4}, {as: AHASHSTP, a1: C_REG, a6: C_SOREG, asmout: type_hashstp, size: 4}, {as: ALXVKQ, a1: C_U5CON, a6: C_VSREG, asmout: type_lxvkq, size: 4}, {as: ALXVP, a1: C_SOREG, a6: C_VSREGP, asmout: type_lxvp, size: 4}, {as: ALXVPX, a1: C_XOREG, a6: C_VSREGP, asmout: type_lxvpx, size: 4}, {as: ALXVRWX, a1: C_XOREG, a6: C_VSREG, asmout: type_lxvrwx, size: 4}, {as: AMTVSRBMI, a1: C_U16CON, a6: C_VREG, asmout: type_mtvsrbmi, size: 4}, {as: AMTVSRWM, a1: C_REG, a6: C_VREG, asmout: type_xscvuqqp, size: 4}, {as: APADDI, a1: C_REG, a3: C_S34CON, a4: C_U1CON, a6: C_REG, asmout: type_paddi, ispfx: true, size: 8}, {as: APEXTD, a1: C_REG, a2: C_REG, a6: C_REG, asmout: type_pextd, size: 4}, {as: APLFS, a1: C_LOREG, a3: C_U1CON, a6: C_FREG, asmout: type_plxssp, ispfx: true, size: 8}, {as: APLQ, a1: C_LOREG, a3: C_U1CON, a6: C_REGP, asmout: type_plxssp, ispfx: true, size: 8}, {as: APLWZ, a1: C_LOREG, a3: C_U1CON, a6: C_REG, asmout: type_plxssp, ispfx: true, size: 8}, {as: APLXSSP, a1: C_LOREG, a3: C_U1CON, a6: C_VREG, asmout: type_plxssp, ispfx: true, size: 8}, {as: APLXV, a1: C_LOREG, a3: C_U1CON, a6: C_VSREG, asmout: type_plxv, ispfx: true, size: 8}, {as: APLXVP, a1: C_LOREG, a3: C_U1CON, a6: C_VSREGP, asmout: type_plxvp, ispfx: true, size: 8}, {as: APMXVF32GERPP, a1: C_VSREG, a2: C_VSREG, a3: C_U4CON, a4: C_U4CON, a6: C_AREG, asmout: type_pmxvf32gerpp, ispfx: true, size: 8}, {as: APMXVF64GERPP, a1: C_VSREGP, a2: C_VSREG, a3: C_U4CON, a4: C_U2CON, a6: C_AREG, asmout: type_pmxvf64gerpp, ispfx: true, size: 8}, {as: APMXVI16GER2SPP, a1: C_VSREG, a2: C_VSREG, a3: C_U4CON, a4: C_U4CON, a5: C_U2CON, a6: C_AREG, asmout: type_pmxvi16ger2spp, ispfx: true, size: 8}, {as: APMXVI4GER8PP, a1: C_VSREG, a2: C_VSREG, a3: C_U4CON, a4: C_U4CON, a5: C_U8CON, a6: C_AREG, asmout: type_pmxvi4ger8pp, ispfx: true, size: 8}, {as: APMXVI8GER4SPP, a1: C_VSREG, a2: C_VSREG, a3: C_U4CON, a4: C_U4CON, a5: C_U4CON, a6: C_AREG, asmout: type_pmxvi8ger4spp, ispfx: true, size: 8}, {as: APNOP, asmout: type_pnop, ispfx: true, size: 8}, {as: APSTFS, a1: C_FREG, a3: C_U1CON, a6: C_LOREG, asmout: type_pstxssp, ispfx: true, size: 8}, {as: APSTQ, a1: C_REGP, a3: C_U1CON, a6: C_LOREG, asmout: type_pstxssp, ispfx: true, size: 8}, {as: APSTW, a1: C_REG, a3: C_U1CON, a6: C_LOREG, asmout: type_pstxssp, ispfx: true, size: 8}, {as: APSTXSSP, a1: C_VREG, a3: C_U1CON, a6: C_LOREG, asmout: type_pstxssp, ispfx: true, size: 8}, {as: APSTXV, a1: C_VSREG, a3: C_U1CON, a6: C_LOREG, asmout: type_pstxv, ispfx: true, size: 8}, {as: APSTXVP, a1: C_VSREGP, a3: C_U1CON, a6: C_LOREG, asmout: type_pstxvp, ispfx: true, size: 8}, {as: ASETNBCR, a1: C_CRBIT, a6: C_REG, asmout: type_setnbcr, size: 4}, {as: ASTXVP, a1: C_VSREGP, a6: C_SOREG, asmout: type_stxvp, size: 4}, {as: ASTXVPX, a1: C_VSREGP, a6: C_XOREG, asmout: type_stxvpx, size: 4}, {as: ASTXVRWX, a1: C_VSREG, a6: C_XOREG, asmout: type_stxvrwx, size: 4}, {as: AVCLRRB, a1: C_VREG, a2: C_REG, a6: C_VREG, asmout: type_xsmincqp, size: 4}, {as: AVCMPUQ, a1: C_VREG, a2: C_VREG, a6: C_CREG, asmout: type_vcmpuq, size: 4}, {as: AVCNTMBW, a1: C_VREG, a3: C_U1CON, a6: C_REG, asmout: type_vcntmbw, size: 4}, {as: AVEXTDUWVRX, a1: C_VREG, a2: C_VREG, a3: C_REG, a6: C_VREG, asmout: type_vmsumcud, size: 4}, {as: AVEXTRACTWM, a1: C_VREG, a6: C_REG, asmout: type_xscvuqqp, size: 4}, {as: AVGNB, a1: C_VREG, a3: C_U3CON, a6: C_REG, asmout: type_vgnb, size: 4}, {as: AVINSW, a1: C_REG, a3: C_U4CON, a6: C_VREG, asmout: type_vinsw, size: 4}, {as: AVINSWRX, a1: C_REG, a2: C_REG, a6: C_VREG, asmout: type_xsmincqp, size: 4}, {as: AVINSWVRX, a1: C_REG, a2: C_VREG, a6: C_VREG, asmout: type_xsmincqp, size: 4}, {as: AVMSUMCUD, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, asmout: type_vmsumcud, size: 4}, {as: AVSRDBI, a1: C_VREG, a2: C_VREG, a3: C_U3CON, a6: C_VREG, asmout: type_vsrdbi, size: 4}, {as: AXSCVUQQP, a1: C_VREG, a6: C_VREG, asmout: type_xscvuqqp, size: 4}, {as: AXSMINCQP, a1: C_VREG, a2: C_VREG, a6: C_VREG, asmout: type_xsmincqp, size: 4}, {as: AXVCVSPBF16, a1: C_VSREG, a6: C_VSREG, asmout: type_xvcvspbf16, size: 4}, {as: AXVI8GER4SPP, a1: C_VSREG, a2: C_VSREG, a6: C_AREG, asmout: type_xvi8ger4spp, size: 4}, {as: AXVTLSBB, a1: C_VSREG, a6: C_CREG, asmout: type_xvtlsbb, size: 4}, {as: AXXBLENDVW, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a6: C_VSREG, asmout: type_xxblendvw, ispfx: true, size: 8}, {as: AXXEVAL, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a4: C_U8CON, a6: C_VSREG, asmout: type_xxeval, ispfx: true, size: 8}, {as: AXXGENPCVWM, a1: C_VREG, a3: C_U5CON, a6: C_VSREG, asmout: type_xxgenpcvwm, size: 4}, {as: AXXPERMX, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a4: C_U3CON, a6: C_VSREG, asmout: type_xxpermx, ispfx: true, size: 8}, {as: AXXSETACCZ, a6: C_AREG, asmout: type_xxsetaccz, size: 4}, {as: AXXSPLTI32DX, a1: C_U1CON, a3: C_U32CON, a6: C_VSREG, asmout: type_xxsplti32dx, ispfx: true, size: 8}, {as: AXXSPLTIW, a1: C_U32CON, a6: C_VSREG, asmout: type_xxspltiw, ispfx: true, size: 8}, } // brw RA,RS func type_brw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 16 // RA o0 |= uint32(p.From.Reg&0x1f) << 21 // RS out[0] = o0 } // hashchkp RB,offset(RA) func type_hashchkp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 11 // RB o0 |= uint32((p.From.Offset>>8)&0x1) << 0 // DX o0 |= uint32((p.From.Offset>>3)&0x1f) << 21 // D o0 |= uint32(p.From.Reg&0x1f) << 16 // RA if p.From.Offset&0xfffffe07 != 0xfffffe00 { c.ctxt.Diag("Constant(%d) must within the range of [-512,-8] in steps of 8\n%v", p.From.Offset, p) } out[0] = o0 } // hashstp RB,offset(RA) func type_hashstp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.From.Reg&0x1f) << 11 // RB o0 |= uint32((p.To.Offset>>8)&0x1) << 0 // DX o0 |= uint32((p.To.Offset>>3)&0x1f) << 21 // D o0 |= uint32(p.To.Reg&0x1f) << 16 // RA if p.To.Offset&0xfffffe07 != 0xfffffe00 { c.ctxt.Diag("Constant(%d) must within the range of [-512,-8] in steps of 8\n%v", p.To.Offset, p) } out[0] = o0 } // lxvkq XT,UIM func type_lxvkq(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.To.Reg>>5)&0x1) << 0 // TX o0 |= uint32(p.To.Reg&0x1f) << 21 // T o0 |= uint32(p.From.Offset&0x1f) << 11 // UIM out[0] = o0 } // lxvp XTp,DQ(RA) func type_lxvp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.To.Reg>>5)&0x1) << 21 // TX o0 |= uint32((p.To.Reg>>1)&0xf) << 22 // Tp o0 |= uint32((p.From.Offset>>4)&0xfff) << 4 // DQ o0 |= uint32(p.From.Reg&0x1f) << 16 // RA if p.From.Offset&0xf != 0 { c.ctxt.Diag("Constant 0x%x (%d) is not a multiple of 16\n%v", p.From.Offset, p.From.Offset, p) } out[0] = o0 } // lxvpx XTp,RA,RB func type_lxvpx(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.To.Reg>>5)&0x1) << 21 // TX o0 |= uint32((p.To.Reg>>1)&0xf) << 22 // Tp o0 |= uint32(p.From.Index&0x1f) << 16 // RA o0 |= uint32(p.From.Reg&0x1f) << 11 // RB out[0] = o0 } // lxvrwx XT,RA,RB func type_lxvrwx(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.To.Reg>>5)&0x1) << 0 // TX o0 |= uint32(p.To.Reg&0x1f) << 21 // T o0 |= uint32(p.From.Index&0x1f) << 16 // RA o0 |= uint32(p.From.Reg&0x1f) << 11 // RB out[0] = o0 } // mtvsrbmi VRT,bm func type_mtvsrbmi(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // VRT o0 |= uint32((p.From.Offset>>6)&0x3ff) << 6 // b0 o0 |= uint32((p.From.Offset>>1)&0x1f) << 16 // b1 o0 |= uint32(p.From.Offset&0x1) << 0 // b2 out[0] = o0 } // paddi RT,RA,SI,R func type_paddi(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32(p.To.Reg&0x1f) << 21 // RT o1 |= uint32(p.From.Reg&0x1f) << 16 // RA o0 |= uint32((p.RestArgs[0].Addr.Offset>>16)&0x3ffff) << 0 // si0 o1 |= uint32(p.RestArgs[0].Addr.Offset&0xffff) << 0 // si1 o0 |= uint32(p.RestArgs[1].Addr.Offset&0x1) << 20 // R out[1] = o1 out[0] = o0 } // pextd RA,RS,RB func type_pextd(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 16 // RA o0 |= uint32(p.From.Reg&0x1f) << 21 // RS o0 |= uint32(p.Reg&0x1f) << 11 // RB out[0] = o0 } // plxssp VRT,D(RA),R func type_plxssp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32(p.To.Reg&0x1f) << 21 // VRT o0 |= uint32((p.From.Offset>>16)&0x3ffff) << 0 // d0 o1 |= uint32(p.From.Offset&0xffff) << 0 // d1 o1 |= uint32(p.From.Reg&0x1f) << 16 // RA o0 |= uint32(p.RestArgs[0].Addr.Offset&0x1) << 20 // R out[1] = o1 out[0] = o0 } // plxv XT,D(RA),R func type_plxv(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.To.Reg>>5)&0x1) << 26 // TX o1 |= uint32(p.To.Reg&0x1f) << 21 // T o0 |= uint32((p.From.Offset>>16)&0x3ffff) << 0 // d0 o1 |= uint32(p.From.Offset&0xffff) << 0 // d1 o1 |= uint32(p.From.Reg&0x1f) << 16 // RA o0 |= uint32(p.RestArgs[0].Addr.Offset&0x1) << 20 // R out[1] = o1 out[0] = o0 } // plxvp XTp,D(RA),R func type_plxvp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.To.Reg>>5)&0x1) << 21 // TX o1 |= uint32((p.To.Reg>>1)&0xf) << 22 // Tp o0 |= uint32((p.From.Offset>>16)&0x3ffff) << 0 // d0 o1 |= uint32(p.From.Offset&0xffff) << 0 // d1 o1 |= uint32(p.From.Reg&0x1f) << 16 // RA o0 |= uint32(p.RestArgs[0].Addr.Offset&0x1) << 20 // R out[1] = o1 out[0] = o0 } // pmxvf32gerpp AT,XA,XB,XMSK,YMSK func type_pmxvf32gerpp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32(p.To.Reg&0x7) << 23 // AT o1 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o1 |= uint32(p.From.Reg&0x1f) << 16 // A o1 |= uint32((p.Reg>>5)&0x1) << 1 // BX o1 |= uint32(p.Reg&0x1f) << 11 // B o0 |= uint32(p.RestArgs[0].Addr.Offset&0xf) << 4 // XMSK o0 |= uint32(p.RestArgs[1].Addr.Offset&0xf) << 0 // YMSK out[1] = o1 out[0] = o0 } // pmxvf64gerpp AT,XAp,XB,XMSK,YMSK func type_pmxvf64gerpp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32(p.To.Reg&0x7) << 23 // AT o1 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o1 |= uint32(p.From.Reg&0x1f) << 16 // Ap o1 |= uint32((p.Reg>>5)&0x1) << 1 // BX o1 |= uint32(p.Reg&0x1f) << 11 // B o0 |= uint32(p.RestArgs[0].Addr.Offset&0xf) << 4 // XMSK o0 |= uint32(p.RestArgs[1].Addr.Offset&0x3) << 2 // YMSK out[1] = o1 out[0] = o0 } // pmxvi16ger2spp AT,XA,XB,XMSK,YMSK,PMSK func type_pmxvi16ger2spp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32(p.To.Reg&0x7) << 23 // AT o1 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o1 |= uint32(p.From.Reg&0x1f) << 16 // A o1 |= uint32((p.Reg>>5)&0x1) << 1 // BX o1 |= uint32(p.Reg&0x1f) << 11 // B o0 |= uint32(p.RestArgs[0].Addr.Offset&0xf) << 4 // XMSK o0 |= uint32(p.RestArgs[1].Addr.Offset&0xf) << 0 // YMSK o0 |= uint32(p.RestArgs[2].Addr.Offset&0x3) << 14 // PMSK out[1] = o1 out[0] = o0 } // pmxvi4ger8pp AT,XA,XB,XMSK,YMSK,PMSK func type_pmxvi4ger8pp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32(p.To.Reg&0x7) << 23 // AT o1 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o1 |= uint32(p.From.Reg&0x1f) << 16 // A o1 |= uint32((p.Reg>>5)&0x1) << 1 // BX o1 |= uint32(p.Reg&0x1f) << 11 // B o0 |= uint32(p.RestArgs[0].Addr.Offset&0xf) << 4 // XMSK o0 |= uint32(p.RestArgs[1].Addr.Offset&0xf) << 0 // YMSK o0 |= uint32(p.RestArgs[2].Addr.Offset&0xff) << 8 // PMSK out[1] = o1 out[0] = o0 } // pmxvi8ger4spp AT,XA,XB,XMSK,YMSK,PMSK func type_pmxvi8ger4spp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32(p.To.Reg&0x7) << 23 // AT o1 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o1 |= uint32(p.From.Reg&0x1f) << 16 // A o1 |= uint32((p.Reg>>5)&0x1) << 1 // BX o1 |= uint32(p.Reg&0x1f) << 11 // B o0 |= uint32(p.RestArgs[0].Addr.Offset&0xf) << 4 // XMSK o0 |= uint32(p.RestArgs[1].Addr.Offset&0xf) << 0 // YMSK o0 |= uint32(p.RestArgs[2].Addr.Offset&0xf) << 12 // PMSK out[1] = o1 out[0] = o0 } // pnop func type_pnop(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] out[1] = o1 out[0] = o0 } // pstxssp VRS,D(RA),R func type_pstxssp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32(p.From.Reg&0x1f) << 21 // VRS o0 |= uint32((p.To.Offset>>16)&0x3ffff) << 0 // d0 o1 |= uint32(p.To.Offset&0xffff) << 0 // d1 o1 |= uint32(p.To.Reg&0x1f) << 16 // RA o0 |= uint32(p.RestArgs[0].Addr.Offset&0x1) << 20 // R out[1] = o1 out[0] = o0 } // pstxv XS,D(RA),R func type_pstxv(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.From.Reg>>5)&0x1) << 26 // SX o1 |= uint32(p.From.Reg&0x1f) << 21 // S o0 |= uint32((p.To.Offset>>16)&0x3ffff) << 0 // d0 o1 |= uint32(p.To.Offset&0xffff) << 0 // d1 o1 |= uint32(p.To.Reg&0x1f) << 16 // RA o0 |= uint32(p.RestArgs[0].Addr.Offset&0x1) << 20 // R out[1] = o1 out[0] = o0 } // pstxvp XSp,D(RA),R func type_pstxvp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.From.Reg>>5)&0x1) << 21 // SX o1 |= uint32((p.From.Reg>>1)&0xf) << 22 // Sp o0 |= uint32((p.To.Offset>>16)&0x3ffff) << 0 // d0 o1 |= uint32(p.To.Offset&0xffff) << 0 // d1 o1 |= uint32(p.To.Reg&0x1f) << 16 // RA o0 |= uint32(p.RestArgs[0].Addr.Offset&0x1) << 20 // R out[1] = o1 out[0] = o0 } // setnbcr RT,BI func type_setnbcr(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // RT o0 |= uint32(p.From.Reg&0x1f) << 16 // BI out[0] = o0 } // stxvp XSp,DQ(RA) func type_stxvp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.From.Reg>>5)&0x1) << 21 // SX o0 |= uint32((p.From.Reg>>1)&0xf) << 22 // Sp o0 |= uint32((p.To.Offset>>4)&0xfff) << 4 // DQ o0 |= uint32(p.To.Reg&0x1f) << 16 // RA if p.To.Offset&0xf != 0 { c.ctxt.Diag("Constant 0x%x (%d) is not a multiple of 16\n%v", p.To.Offset, p.To.Offset, p) } out[0] = o0 } // stxvpx XSp,RA,RB func type_stxvpx(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.From.Reg>>5)&0x1) << 21 // SX o0 |= uint32((p.From.Reg>>1)&0xf) << 22 // Sp o0 |= uint32(p.To.Index&0x1f) << 16 // RA o0 |= uint32(p.To.Reg&0x1f) << 11 // RB out[0] = o0 } // stxvrwx XS,RA,RB func type_stxvrwx(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.From.Reg>>5)&0x1) << 0 // SX o0 |= uint32(p.From.Reg&0x1f) << 21 // S o0 |= uint32(p.To.Index&0x1f) << 16 // RA o0 |= uint32(p.To.Reg&0x1f) << 11 // RB out[0] = o0 } // vcmpuq BF,VRA,VRB func type_vcmpuq(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x7) << 23 // BF o0 |= uint32(p.From.Reg&0x1f) << 16 // VRA o0 |= uint32(p.Reg&0x1f) << 11 // VRB out[0] = o0 } // vcntmbw RT,VRB,MP func type_vcntmbw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // RT o0 |= uint32(p.From.Reg&0x1f) << 11 // VRB o0 |= uint32(p.RestArgs[0].Addr.Offset&0x1) << 16 // MP out[0] = o0 } // vgnb RT,VRB,N func type_vgnb(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // RT o0 |= uint32(p.From.Reg&0x1f) << 11 // VRB o0 |= uint32(p.RestArgs[0].Addr.Offset&0x7) << 16 // N out[0] = o0 } // vinsw VRT,RB,UIM func type_vinsw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // VRT o0 |= uint32(p.From.Reg&0x1f) << 11 // RB o0 |= uint32(p.RestArgs[0].Addr.Offset&0xf) << 16 // UIM out[0] = o0 } // vmsumcud VRT,VRA,VRB,VRC func type_vmsumcud(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // VRT o0 |= uint32(p.From.Reg&0x1f) << 16 // VRA o0 |= uint32(p.Reg&0x1f) << 11 // VRB o0 |= uint32(p.RestArgs[0].Addr.Reg&0x1f) << 6 // VRC out[0] = o0 } // vsrdbi VRT,VRA,VRB,SH func type_vsrdbi(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // VRT o0 |= uint32(p.From.Reg&0x1f) << 16 // VRA o0 |= uint32(p.Reg&0x1f) << 11 // VRB o0 |= uint32(p.RestArgs[0].Addr.Offset&0x7) << 6 // SH out[0] = o0 } // xscvuqqp VRT,VRB func type_xscvuqqp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // VRT o0 |= uint32(p.From.Reg&0x1f) << 11 // VRB out[0] = o0 } // xsmincqp VRT,VRA,VRB func type_xsmincqp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x1f) << 21 // VRT o0 |= uint32(p.From.Reg&0x1f) << 16 // VRA o0 |= uint32(p.Reg&0x1f) << 11 // VRB out[0] = o0 } // xvcvspbf16 XT,XB func type_xvcvspbf16(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.To.Reg>>5)&0x1) << 0 // TX o0 |= uint32(p.To.Reg&0x1f) << 21 // T o0 |= uint32((p.From.Reg>>5)&0x1) << 1 // BX o0 |= uint32(p.From.Reg&0x1f) << 11 // B out[0] = o0 } // xvi8ger4spp AT,XA,XB func type_xvi8ger4spp(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x7) << 23 // AT o0 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o0 |= uint32(p.From.Reg&0x1f) << 16 // A o0 |= uint32((p.Reg>>5)&0x1) << 1 // BX o0 |= uint32(p.Reg&0x1f) << 11 // B out[0] = o0 } // xvtlsbb BF,XB func type_xvtlsbb(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x7) << 23 // BF o0 |= uint32((p.From.Reg>>5)&0x1) << 1 // BX o0 |= uint32(p.From.Reg&0x1f) << 11 // B out[0] = o0 } // xxblendvw XT,XA,XB,XC func type_xxblendvw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.To.Reg>>5)&0x1) << 0 // TX o1 |= uint32(p.To.Reg&0x1f) << 21 // T o1 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o1 |= uint32(p.From.Reg&0x1f) << 16 // A o1 |= uint32((p.Reg>>5)&0x1) << 1 // BX o1 |= uint32(p.Reg&0x1f) << 11 // B o1 |= uint32((p.RestArgs[0].Addr.Reg>>5)&0x1) << 3 // CX o1 |= uint32(p.RestArgs[0].Addr.Reg&0x1f) << 6 // C out[1] = o1 out[0] = o0 } // xxeval XT,XA,XB,XC,IMM func type_xxeval(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.To.Reg>>5)&0x1) << 0 // TX o1 |= uint32(p.To.Reg&0x1f) << 21 // T o1 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o1 |= uint32(p.From.Reg&0x1f) << 16 // A o1 |= uint32((p.Reg>>5)&0x1) << 1 // BX o1 |= uint32(p.Reg&0x1f) << 11 // B o1 |= uint32((p.RestArgs[0].Addr.Reg>>5)&0x1) << 3 // CX o1 |= uint32(p.RestArgs[0].Addr.Reg&0x1f) << 6 // C o0 |= uint32(p.RestArgs[1].Addr.Offset&0xff) << 0 // IMM out[1] = o1 out[0] = o0 } // xxgenpcvwm XT,VRB,IMM func type_xxgenpcvwm(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32((p.To.Reg>>5)&0x1) << 0 // TX o0 |= uint32(p.To.Reg&0x1f) << 21 // T o0 |= uint32(p.From.Reg&0x1f) << 11 // VRB o0 |= uint32(p.RestArgs[0].Addr.Offset&0x1f) << 16 // IMM out[0] = o0 } // xxpermx XT,XA,XB,XC,UIM func type_xxpermx(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.To.Reg>>5)&0x1) << 0 // TX o1 |= uint32(p.To.Reg&0x1f) << 21 // T o1 |= uint32((p.From.Reg>>5)&0x1) << 2 // AX o1 |= uint32(p.From.Reg&0x1f) << 16 // A o1 |= uint32((p.Reg>>5)&0x1) << 1 // BX o1 |= uint32(p.Reg&0x1f) << 11 // B o1 |= uint32((p.RestArgs[0].Addr.Reg>>5)&0x1) << 3 // CX o1 |= uint32(p.RestArgs[0].Addr.Reg&0x1f) << 6 // C o0 |= uint32(p.RestArgs[1].Addr.Offset&0x7) << 0 // UIM out[1] = o1 out[0] = o0 } // xxsetaccz AT func type_xxsetaccz(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenOpcodes[p.As-AXXSETACCZ] o0 |= uint32(p.To.Reg&0x7) << 23 // AT out[0] = o0 } // xxsplti32dx XT,IX,IMM32 func type_xxsplti32dx(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.To.Reg>>5)&0x1) << 16 // TX o1 |= uint32(p.To.Reg&0x1f) << 21 // T o1 |= uint32(p.From.Offset&0x1) << 17 // IX o0 |= uint32((p.RestArgs[0].Addr.Offset>>16)&0xffff) << 0 // imm0 o1 |= uint32(p.RestArgs[0].Addr.Offset&0xffff) << 0 // imm1 out[1] = o1 out[0] = o0 } // xxspltiw XT,IMM32 func type_xxspltiw(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) { o0 := GenPfxOpcodes[p.As-AXXSPLTIW] o1 := GenOpcodes[p.As-AXXSETACCZ] o1 |= uint32((p.To.Reg>>5)&0x1) << 16 // TX o1 |= uint32(p.To.Reg&0x1f) << 21 // T o0 |= uint32((p.From.Offset>>16)&0xffff) << 0 // imm0 o1 |= uint32(p.From.Offset&0xffff) << 0 // imm1 out[1] = o1 out[0] = o0 } func opsetGen(from obj.As) bool { r0 := from & obj.AMask switch from { case ABRW: opset(ABRH, r0) opset(ABRD, r0) case ADCFFIXQQ: case ADCTFIXQQ: case AHASHCHKP: opset(AHASHCHK, r0) case AHASHSTP: opset(AHASHST, r0) case ALXVKQ: case ALXVP: case ALXVPX: case ALXVRWX: opset(ALXVRHX, r0) opset(ALXVRDX, r0) opset(ALXVRBX, r0) case AMTVSRBMI: case AMTVSRWM: opset(AMTVSRQM, r0) opset(AMTVSRHM, r0) opset(AMTVSRDM, r0) opset(AMTVSRBM, r0) case APADDI: case APEXTD: opset(APDEPD, r0) opset(ACNTTZDM, r0) opset(ACNTLZDM, r0) opset(ACFUGED, r0) case APLFS: opset(APLFD, r0) case APLQ: case APLWZ: opset(APLWA, r0) opset(APLHZ, r0) opset(APLHA, r0) opset(APLD, r0) opset(APLBZ, r0) case APLXSSP: opset(APLXSD, r0) case APLXV: case APLXVP: case APMXVF32GERPP: opset(APMXVF32GERPN, r0) opset(APMXVF32GERNP, r0) opset(APMXVF32GERNN, r0) opset(APMXVF32GER, r0) case APMXVF64GERPP: opset(APMXVF64GERPN, r0) opset(APMXVF64GERNP, r0) opset(APMXVF64GERNN, r0) opset(APMXVF64GER, r0) case APMXVI16GER2SPP: opset(APMXVI16GER2S, r0) opset(APMXVI16GER2PP, r0) opset(APMXVI16GER2, r0) opset(APMXVF16GER2PP, r0) opset(APMXVF16GER2PN, r0) opset(APMXVF16GER2NP, r0) opset(APMXVF16GER2NN, r0) opset(APMXVF16GER2, r0) opset(APMXVBF16GER2PP, r0) opset(APMXVBF16GER2PN, r0) opset(APMXVBF16GER2NP, r0) opset(APMXVBF16GER2NN, r0) opset(APMXVBF16GER2, r0) case APMXVI4GER8PP: opset(APMXVI4GER8, r0) case APMXVI8GER4SPP: opset(APMXVI8GER4PP, r0) opset(APMXVI8GER4, r0) case APNOP: case APSTFS: opset(APSTFD, r0) case APSTQ: case APSTW: opset(APSTH, r0) opset(APSTD, r0) opset(APSTB, r0) case APSTXSSP: opset(APSTXSD, r0) case APSTXV: case APSTXVP: case ASETNBCR: opset(ASETNBC, r0) opset(ASETBCR, r0) opset(ASETBC, r0) case ASTXVP: case ASTXVPX: case ASTXVRWX: opset(ASTXVRHX, r0) opset(ASTXVRDX, r0) opset(ASTXVRBX, r0) case AVCLRRB: opset(AVCLRLB, r0) case AVCMPUQ: opset(AVCMPSQ, r0) case AVCNTMBW: opset(AVCNTMBH, r0) opset(AVCNTMBD, r0) opset(AVCNTMBB, r0) case AVEXTDUWVRX: opset(AVEXTDUWVLX, r0) opset(AVEXTDUHVRX, r0) opset(AVEXTDUHVLX, r0) opset(AVEXTDUBVRX, r0) opset(AVEXTDUBVLX, r0) opset(AVEXTDDVRX, r0) opset(AVEXTDDVLX, r0) case AVEXTRACTWM: opset(AVEXTRACTQM, r0) opset(AVEXTRACTHM, r0) opset(AVEXTRACTDM, r0) opset(AVEXTRACTBM, r0) case AVGNB: case AVINSW: opset(AVINSD, r0) case AVINSWRX: opset(AVINSWLX, r0) opset(AVINSHRX, r0) opset(AVINSHLX, r0) opset(AVINSDRX, r0) opset(AVINSDLX, r0) opset(AVINSBRX, r0) opset(AVINSBLX, r0) case AVINSWVRX: opset(AVINSWVLX, r0) opset(AVINSHVRX, r0) opset(AVINSHVLX, r0) opset(AVINSBVRX, r0) opset(AVINSBVLX, r0) case AVMSUMCUD: case AVSRDBI: opset(AVSLDBI, r0) case AXSCVUQQP: opset(AXSCVSQQP, r0) opset(AXSCVQPUQZ, r0) opset(AXSCVQPSQZ, r0) opset(AVSTRIHRCC, r0) opset(AVSTRIHR, r0) opset(AVSTRIHLCC, r0) opset(AVSTRIHL, r0) opset(AVSTRIBRCC, r0) opset(AVSTRIBR, r0) opset(AVSTRIBLCC, r0) opset(AVSTRIBL, r0) opset(AVEXTSD2Q, r0) opset(AVEXPANDWM, r0) opset(AVEXPANDQM, r0) opset(AVEXPANDHM, r0) opset(AVEXPANDDM, r0) opset(AVEXPANDBM, r0) case AXSMINCQP: opset(AXSMAXCQP, r0) opset(AXSCMPGTQP, r0) opset(AXSCMPGEQP, r0) opset(AXSCMPEQQP, r0) opset(AVSRQ, r0) opset(AVSRAQ, r0) opset(AVSLQ, r0) opset(AVRLQNM, r0) opset(AVRLQMI, r0) opset(AVRLQ, r0) opset(AVPEXTD, r0) opset(AVPDEPD, r0) opset(AVMULOUD, r0) opset(AVMULOSD, r0) opset(AVMULLD, r0) opset(AVMULHUW, r0) opset(AVMULHUD, r0) opset(AVMULHSW, r0) opset(AVMULHSD, r0) opset(AVMULEUD, r0) opset(AVMULESD, r0) opset(AVMODUW, r0) opset(AVMODUQ, r0) opset(AVMODUD, r0) opset(AVMODSW, r0) opset(AVMODSQ, r0) opset(AVMODSD, r0) opset(AVDIVUW, r0) opset(AVDIVUQ, r0) opset(AVDIVUD, r0) opset(AVDIVSW, r0) opset(AVDIVSQ, r0) opset(AVDIVSD, r0) opset(AVDIVEUW, r0) opset(AVDIVEUQ, r0) opset(AVDIVEUD, r0) opset(AVDIVESW, r0) opset(AVDIVESQ, r0) opset(AVDIVESD, r0) opset(AVCTZDM, r0) opset(AVCMPGTUQCC, r0) opset(AVCMPGTUQ, r0) opset(AVCMPGTSQCC, r0) opset(AVCMPGTSQ, r0) opset(AVCMPEQUQCC, r0) opset(AVCMPEQUQ, r0) opset(AVCLZDM, r0) opset(AVCFUGED, r0) case AXVCVSPBF16: opset(AXVCVBF16SPN, r0) case AXVI8GER4SPP: opset(AXVI8GER4PP, r0) opset(AXVI8GER4, r0) opset(AXVI4GER8PP, r0) opset(AXVI4GER8, r0) opset(AXVI16GER2SPP, r0) opset(AXVI16GER2S, r0) opset(AXVI16GER2PP, r0) opset(AXVI16GER2, r0) opset(AXVF64GERPP, r0) opset(AXVF64GERPN, r0) opset(AXVF64GERNP, r0) opset(AXVF64GERNN, r0) opset(AXVF64GER, r0) opset(AXVF32GERPP, r0) opset(AXVF32GERPN, r0) opset(AXVF32GERNP, r0) opset(AXVF32GERNN, r0) opset(AXVF32GER, r0) opset(AXVF16GER2PP, r0) opset(AXVF16GER2PN, r0) opset(AXVF16GER2NP, r0) opset(AXVF16GER2NN, r0) opset(AXVF16GER2, r0) opset(AXVBF16GER2PP, r0) opset(AXVBF16GER2PN, r0) opset(AXVBF16GER2NP, r0) opset(AXVBF16GER2NN, r0) opset(AXVBF16GER2, r0) case AXVTLSBB: case AXXBLENDVW: opset(AXXBLENDVH, r0) opset(AXXBLENDVD, r0) opset(AXXBLENDVB, r0) case AXXEVAL: case AXXGENPCVWM: opset(AXXGENPCVHM, r0) opset(AXXGENPCVDM, r0) opset(AXXGENPCVBM, r0) case AXXPERMX: case AXXSETACCZ: opset(AXXMTACC, r0) opset(AXXMFACC, r0) case AXXSPLTI32DX: case AXXSPLTIW: opset(AXXSPLTIDP, r0) default: return false } return true }